From eeb161ec51e04be60164d3aae93fe1f62d00ecfc Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Tue, 19 Mar 2019 21:33:52 -0400 Subject: [PATCH] Converts the prefetch queue into a 32-bit quantity. --- .../Implementation/68000Implementation.hpp | 24 +++++++++---------- .../68000/Implementation/68000Storage.cpp | 2 +- .../68000/Implementation/68000Storage.hpp | 2 +- 3 files changed, 14 insertions(+), 14 deletions(-) diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp index a50b2d9a9..ef8574376 100644 --- a/Processors/68000/Implementation/68000Implementation.hpp +++ b/Processors/68000/Implementation/68000Implementation.hpp @@ -45,7 +45,7 @@ template void Processor: case BusStep::Action::IncrementProgramCounter: program_counter_.full += 2; break; case BusStep::Action::AdvancePrefetch: - prefetch_queue_[0] = prefetch_queue_[1]; + prefetch_queue_.halves.high = prefetch_queue_.halves.low; break; } @@ -69,7 +69,7 @@ template void Processor: // TODO: unless an interrupt is pending, or the trap flag is set. - const uint16_t next_instruction = prefetch_queue_[0].full; + const uint16_t next_instruction = prefetch_queue_.halves.high; if(!instructions[next_instruction].micro_operations) { // TODO: once all instructions are implemnted, this should be an instruction error. std::cerr << "68000 Abilities exhausted; can't manage instruction " << std::hex << next_instruction << std::endl; @@ -205,16 +205,16 @@ template void Processor: break; case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask: - effective_address_[0] = int16_t(prefetch_queue_[0].full) + active_program_->source->full; + effective_address_[0] = int16_t(prefetch_queue_.halves.high) + active_program_->source->full; break; case int(MicroOp::Action::CalcD16An) | MicroOp::DestinationMask: - effective_address_[1] = int16_t(prefetch_queue_[0].full) + active_program_->destination->full; + effective_address_[1] = int16_t(prefetch_queue_.halves.high) + active_program_->destination->full; break; case int(MicroOp::Action::CalcD16An) | MicroOp::SourceMask | MicroOp::DestinationMask: - effective_address_[0] = int16_t(prefetch_queue_[0].full) + active_program_->source->full; - effective_address_[1] = int16_t(prefetch_queue_[1].full) + active_program_->destination->full; + effective_address_[0] = int16_t(prefetch_queue_.halves.high) + active_program_->source->full; + effective_address_[1] = int16_t(prefetch_queue_.halves.low) + active_program_->destination->full; break; // TODO: permit as below for DestinationMask and SourceMask|DestinationMask; would prefer to test first. @@ -230,26 +230,26 @@ template void Processor: } \ } case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask: { - CalculateD8AnXn(prefetch_queue_[0], active_program_->source, effective_address_[0]); + CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->source, effective_address_[0]); } break; case int(MicroOp::Action::CalcD8AnXn) | MicroOp::DestinationMask: { - CalculateD8AnXn(prefetch_queue_[0], active_program_->destination, effective_address_[1]); + CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->destination, effective_address_[1]); } break; case int(MicroOp::Action::CalcD8AnXn) | MicroOp::SourceMask | MicroOp::DestinationMask: { - CalculateD8AnXn(prefetch_queue_[0], active_program_->source, effective_address_[0]); - CalculateD8AnXn(prefetch_queue_[1], active_program_->destination, effective_address_[1]); + CalculateD8AnXn(prefetch_queue_.halves.high, active_program_->source, effective_address_[0]); + CalculateD8AnXn(prefetch_queue_.halves.low, active_program_->destination, effective_address_[1]); } break; #undef CalculateD8AnXn case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::SourceMask: - bus_data_[0] = (prefetch_queue_[0] << 16) | prefetch_queue_[1]; + bus_data_[0] = prefetch_queue_.full; break; case int(MicroOp::Action::AssembleWordFromPrefetch) | MicroOp::DestinationMask: - bus_data_[1] = (prefetch_queue_[0] << 16) | prefetch_queue_[1]; + bus_data_[1] = prefetch_queue_.full; break; } diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp index 541637660..1d9958e9e 100644 --- a/Processors/68000/Implementation/68000Storage.cpp +++ b/Processors/68000/Implementation/68000Storage.cpp @@ -128,7 +128,7 @@ struct ProcessorStorageConstructor { step.microcycle.length = HalfCycles(5); step.microcycle.operation = Microcycle::NewAddress | Microcycle::Read | Microcycle::IsProgram; step.microcycle.address = &storage_.program_counter_.full; - step.microcycle.value = &storage_.prefetch_queue_[1]; + step.microcycle.value = &storage_.prefetch_queue_.halves.low; step.action = Action::AdvancePrefetch; steps.push_back(step); diff --git a/Processors/68000/Implementation/68000Storage.hpp b/Processors/68000/Implementation/68000Storage.hpp index 588d29a14..7f0daa33e 100644 --- a/Processors/68000/Implementation/68000Storage.hpp +++ b/Processors/68000/Implementation/68000Storage.hpp @@ -21,7 +21,7 @@ class ProcessorStorage { RegisterPair32 stack_pointers_[2]; // [0] = user stack pointer; [1] = supervisor; the values from here // are copied into/out of address_[7] upon mode switches. - RegisterPair16 prefetch_queue_[2]; + RegisterPair32 prefetch_queue_; // Each word will go into the low part of the word, then proceed upward. bool dtack_ = true; // Various status bits.