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Imports first part of AND tests.
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@ -26,6 +26,174 @@
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_machine.reset();
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}
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// MARK: AND
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- (void)testANDb_Dn {
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_machine->set_program({
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0xc604 // AND.b D4, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54ff7856;
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state.data[4] = 0x9853abcd;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54ff7844);
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XCTAssertEqual(state.data[4], 0x9853abcd);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(_machine->get_cycle_count(), 4);
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}
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- (void)testANDw_Dn {
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_machine->set_program({
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0xc644 // AND.w D4, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.data[4] = 0x9853fbcd;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff844);
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XCTAssertEqual(state.data[4], 0x9853fbcd);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
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XCTAssertEqual(_machine->get_cycle_count(), 4);
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}
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- (void)testANDl_Dn {
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_machine->set_program({
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0xc684 // AND.l D4, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.data[4] = 0x9853fbcd;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x1053f844);
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XCTAssertEqual(state.data[4], 0x9853fbcd);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(_machine->get_cycle_count(), 8);
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}
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- (void)performANDx_Ind:(uint16_t)opcode {
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_machine->set_program({
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opcode
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x3000) = 0x0053;
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*_machine->ram_at(0x3002) = 0xfb00;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(*_machine->ram_at(0x3000), 0x0053);
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XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb00);
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XCTAssertEqual(state.address[4], 0x3000);
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}
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- (void)testANDb_Ind {
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[self performANDx_Ind:0xc614]; // AND.b (A4), D3
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff800);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
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XCTAssertEqual(_machine->get_cycle_count(), 8);
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}
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- (void)testANDw_Ind {
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[self performANDx_Ind:0xc654]; // AND.w (A4), D3
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54ff0052);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(_machine->get_cycle_count(), 8);
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}
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- (void)testANDl_Ind {
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[self performANDx_Ind:0xc694]; // AND.l (A4), D3
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x0053f800);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(_machine->get_cycle_count(), 14);
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}
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- (void)performANDx_PostInc:(uint16_t)opcode {
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_machine->set_program({
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opcode // AND.B (A4)+, D3
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});
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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state.address[4] = 0x3000;
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*_machine->ram_at(0x3000) = 0x0053;
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*_machine->ram_at(0x3002) = 0xfb00;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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}
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- (void)testANDb_PostInc_A4 {
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[self performANDx_PostInc:0xc61c]; // AND.B (A4)+, D3
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff800);
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XCTAssertEqual(state.address[4], 0x3001);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
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XCTAssertEqual(_machine->get_cycle_count(), 8);
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}
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- (void)testANDb_PostInc_A7 {
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_machine->set_program({
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0xc61f // AND.B (A7)+, D3
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});
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_machine->set_initial_stack_pointer(0x3000);
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auto state = _machine->get_processor_state();
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state.data[3] = 0x54fff856;
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*_machine->ram_at(0x3000) = 0x0053;
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*_machine->ram_at(0x3002) = 0xfb00;
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_machine->set_processor_state(state);
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_machine->run_for_instructions(1);
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state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54fff800);
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XCTAssertEqual(state.stack_pointer(), 0x3002);
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XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
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XCTAssertEqual(_machine->get_cycle_count(), 8);
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}
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- (void)testANDw_PostInc_A4 {
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[self performANDx_PostInc:0xc65c]; // AND.w (A4)+, D3
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x54ff0052);
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XCTAssertEqual(state.address[4], 0x3002);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(_machine->get_cycle_count(), 8);
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}
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- (void)testANDl_PostInc_A4 {
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[self performANDx_PostInc:0xc69c]; // AND.l (A4)+, D3
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const auto state = _machine->get_processor_state();
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XCTAssertEqual(state.data[3], 0x0053f800);
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XCTAssertEqual(state.address[4], 0x3004);
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XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
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XCTAssertEqual(_machine->get_cycle_count(), 14);
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}
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// Omitted: address error test.
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// MARK: BCHG
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- (void)performBCHGD0D1:(uint32_t)d1 {
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