From efb854ddfa0556affdaae2a9a242c1dad2942275 Mon Sep 17 00:00:00 2001
From: Thomas Harte <thomas.harte@gmail.com>
Date: Thu, 19 Oct 2023 14:40:03 -0400
Subject: [PATCH] Fix repetition. Sufficient for tests.

---
 .../Implementation/PerformImplementation.hpp  | 18 +++++++-----
 OSBindings/Mac/Clock SignalTests/8088Tests.mm | 28 +++++++++++++------
 2 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/InstructionSets/x86/Implementation/PerformImplementation.hpp b/InstructionSets/x86/Implementation/PerformImplementation.hpp
index ae3449635..9f65125b8 100644
--- a/InstructionSets/x86/Implementation/PerformImplementation.hpp
+++ b/InstructionSets/x86/Implementation/PerformImplementation.hpp
@@ -1401,18 +1401,22 @@ void cmps(const InstructionT &instruction, MemoryT &memory, RegistersT &register
 	}
 
 	Source source_segment = instruction.segment_override();
-	if(source_segment == Source::None) source_segment = Source::DS;
+	if(source_segment == Source::None) {
+		source_segment = Source::DS;
+	} else {
+		printf("");
+	}
 
 	if constexpr (std::is_same_v<AddressT, uint16_t>) {
-		IntT source = memory.template access<IntT>(source_segment, registers.si());
-		IntT destination = memory.template access<IntT>(Source::ES, registers.di());
-		Primitive::sub<false, false>(destination, source, status);
+		IntT lhs = memory.template access<IntT>(source_segment, registers.si());
+		IntT rhs = memory.template access<IntT>(Source::ES, registers.di());
+		Primitive::sub<false, false>(lhs, rhs, status);
 		registers.si() += status.direction<AddressT>();
 		registers.di() += status.direction<AddressT>();
 	} else {
-		IntT source = memory.template access<IntT>(source_segment, registers.esi());
-		IntT destination = memory.template access<IntT>(Source::ES, registers.edi());
-		Primitive::sub<false, false>(destination, source, status);
+		IntT lhs = memory.template access<IntT>(source_segment, registers.esi());
+		IntT rhs = memory.template access<IntT>(Source::ES, registers.edi());
+		Primitive::sub<false, false>(lhs, rhs, status);
 		registers.esi() += status.direction<AddressT>();
 		registers.edi() += status.direction<AddressT>();
 	}
diff --git a/OSBindings/Mac/Clock SignalTests/8088Tests.mm b/OSBindings/Mac/Clock SignalTests/8088Tests.mm
index fa3adf2dd..3c83b3602 100644
--- a/OSBindings/Mac/Clock SignalTests/8088Tests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/8088Tests.mm	
@@ -230,14 +230,21 @@ class FlowController {
 		void halt() {}
 		void wait() {}
 
+		void begin_instruction() {
+			should_repeat_ = false;
+		}
 		void repeat_last() {
-			// TODO.
+			should_repeat_ = true;
+		}
+		bool should_repeat() const {
+			return should_repeat_;
 		}
 
 	private:
 		Memory &memory_;
 		Registers &registers_;
 		Status &status_;
+		bool should_repeat_ = false;
 
 		void push(uint16_t value, bool is_flags = false) {
 			// Perform the push in two steps because it's possible for SP to underflow, and so that FlagsL and
@@ -708,14 +715,17 @@ struct FailedExecution {
 
 	// Execute instruction.
 	execution_support.registers.ip_ += decoded.first;
-	InstructionSet::x86::perform<InstructionSet::x86::Model::i8086>(
-		decoded.second,
-		execution_support.status,
-		execution_support.flow_controller,
-		execution_support.registers,
-		execution_support.memory,
-		execution_support.io
-	);
+	do {
+		execution_support.flow_controller.begin_instruction();
+		InstructionSet::x86::perform<InstructionSet::x86::Model::i8086>(
+			decoded.second,
+			execution_support.status,
+			execution_support.flow_controller,
+			execution_support.registers,
+			execution_support.memory,
+			execution_support.io
+		);
+	} while (execution_support.flow_controller.should_repeat());
 
 	// Compare final state.
 	Registers intended_registers;