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Adjust 65c02 STA abs,x behaviour.

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Thomas Harte 2023-11-29 15:32:02 -05:00
parent 66b95a8b54
commit f25aaf2bb3
3 changed files with 23 additions and 1 deletions
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15
Processors/6502/Implementation/6502Implementation.hpp
View File

@ -544,6 +544,21 @@ template <Personality personality, typename T, bool uses_ready_line> void Proces
break; break;
} }
continue; continue;
case CycleAddXToAddressLowReadSTA:
next_address_.full = address_.full + x_;
address_.halves.low = next_address_.halves.low;
// Cf. https://groups.google.com/g/comp.sys.apple2/c/RuTGaRxu5Iw/m/uyFLEsF8ceIJ
//
// STA abs,X has been fixed for the PX (page-crossing) case by adding a dummy read of the
// program counter, so the change was rW -> W. In the non-PX case it still reads the destination
// address, so there is no change: RW -> RW.
if(!is_65c02(personality) || next_address_.full == address_.full) {
throwaway_read(address_.full);
} else {
throwaway_read(pc_.full - 1);
}
break;
case CycleAddXToAddressLowRead: case CycleAddXToAddressLowRead:
next_address_.full = address_.full + x_; next_address_.full = address_.full + x_;
address_.halves.low = next_address_.halves.low; address_.halves.low = next_address_.halves.low;

4
Processors/6502/Implementation/6502Storage.cpp
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@ -18,6 +18,7 @@ using namespace CPU::MOS6502;
#define AbsoluteXr CycleLoadAddressAbsolute, CycleAddXToAddressLow, OperationCorrectAddressHigh #define AbsoluteXr CycleLoadAddressAbsolute, CycleAddXToAddressLow, OperationCorrectAddressHigh
#define AbsoluteYr CycleLoadAddressAbsolute, CycleAddYToAddressLow, OperationCorrectAddressHigh #define AbsoluteYr CycleLoadAddressAbsolute, CycleAddYToAddressLow, OperationCorrectAddressHigh
#define AbsoluteXw CycleLoadAddressAbsolute, CycleAddXToAddressLowRead, OperationCorrectAddressHigh #define AbsoluteXw CycleLoadAddressAbsolute, CycleAddXToAddressLowRead, OperationCorrectAddressHigh
#define AbsoluteXwSTA CycleLoadAddressAbsolute, CycleAddXToAddressLowReadSTA, OperationCorrectAddressHigh
#define AbsoluteYw CycleLoadAddressAbsolute, CycleAddYToAddressLowRead, OperationCorrectAddressHigh #define AbsoluteYw CycleLoadAddressAbsolute, CycleAddYToAddressLowRead, OperationCorrectAddressHigh
#define Zero OperationLoadAddressZeroPage #define Zero OperationLoadAddressZeroPage
#define ZeroX CycleLoadAddessZeroX #define ZeroX CycleLoadAddessZeroX
@ -43,6 +44,7 @@ using namespace CPU::MOS6502;
#define AbsoluteWrite(op) Program(Absolute, Write(op)) #define AbsoluteWrite(op) Program(Absolute, Write(op))
#define AbsoluteXWrite(op) Program(AbsoluteXw, Write(op)) #define AbsoluteXWrite(op) Program(AbsoluteXw, Write(op))
#define AbsoluteXWriteSTA(op) Program(AbsoluteXwSTA, Write(op))
#define AbsoluteYWrite(op) Program(AbsoluteYw, Write(op)) #define AbsoluteYWrite(op) Program(AbsoluteYw, Write(op))
#define ZeroWrite(op) Program(Zero, Write(op)) #define ZeroWrite(op) Program(Zero, Write(op))
#define ZeroXWrite(op) Program(ZeroX, Write(op)) #define ZeroXWrite(op) Program(ZeroX, Write(op))
@ -162,7 +164,7 @@ ProcessorStorage::ProcessorStorage(Personality personality) {
/* 0x96 STX zpg, y */ ZeroYWrite(OperationSTX), /* 0x97 SAX zpg, y */ ZeroYWrite(OperationSAX), /* 0x96 STX zpg, y */ ZeroYWrite(OperationSTX), /* 0x97 SAX zpg, y */ ZeroYWrite(OperationSAX),
/* 0x98 TYA */ Program(OperationTYA), /* 0x99 STA abs, y */ AbsoluteYWrite(OperationSTA), /* 0x98 TYA */ Program(OperationTYA), /* 0x99 STA abs, y */ AbsoluteYWrite(OperationSTA),
/* 0x9a TXS */ Program(OperationTXS), /* 0x9b SHS abs, y */ AbsoluteYWrite(OperationSHS), /* 0x9a TXS */ Program(OperationTXS), /* 0x9b SHS abs, y */ AbsoluteYWrite(OperationSHS),
/* 0x9c SHY abs, x */ AbsoluteXWrite(OperationSHY), /* 0x9d STA abs, x */ AbsoluteXWrite(OperationSTA), /* 0x9c SHY abs, x */ AbsoluteXWrite(OperationSHY), /* 0x9d STA abs, x */ AbsoluteXWriteSTA(OperationSTA),
/* 0x9e SHX abs, y */ AbsoluteYWrite(OperationSHX), /* 0x9f SHA abs, y */ AbsoluteYWrite(OperationSHA), /* 0x9e SHX abs, y */ AbsoluteYWrite(OperationSHX), /* 0x9f SHA abs, y */ AbsoluteYWrite(OperationSHA),
/* 0xa0 LDY # */ Immediate(OperationLDY), /* 0xa1 LDA x, ind */ IndexedIndirectRead(OperationLDA), /* 0xa0 LDY # */ Immediate(OperationLDY), /* 0xa1 LDA x, ind */ IndexedIndirectRead(OperationLDA),
/* 0xa2 LDX # */ Immediate(OperationLDX), /* 0xa3 LAX x, ind */ IndexedIndirectRead(OperationLAX), /* 0xa2 LDX # */ Immediate(OperationLDX), /* 0xa3 LAX x, ind */ IndexedIndirectRead(OperationLAX),

5
Processors/6502/Implementation/6502Storage.hpp
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@ -77,6 +77,11 @@ class ProcessorStorage {
CycleAddYToAddressLowRead, // calculates address_ + y and stores it to next_address; copies next_address.l back to address_.l; 6502: schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1 CycleAddYToAddressLowRead, // calculates address_ + y and stores it to next_address; copies next_address.l back to address_.l; 6502: schedules a throwaway read from address_; 65C02: schedules a throaway read from PC-1
OperationCorrectAddressHigh, // copies next_address_ to address_ OperationCorrectAddressHigh, // copies next_address_ to address_
// Implements 65c02-compatible version of CycleAddXToAddressLowRead specialised for STA; on that processor
// a non-page-crossing `STA abs, x` acts exactly like a 6502, doing a read of the target address before
// the write, but a page-crossing store instead performs throaway read from PC-1.
CycleAddXToAddressLowReadSTA,
OperationIncrementPC, // increments the PC OperationIncrementPC, // increments the PC
CycleFetchOperandFromAddress, // fetches operand_ from address_ CycleFetchOperandFromAddress, // fetches operand_ from address_
CycleWriteOperandToAddress, // writes operand_ to address_ CycleWriteOperandToAddress, // writes operand_ to address_