diff --git a/Processors/68000/Implementation/68000Implementation.hpp b/Processors/68000/Implementation/68000Implementation.hpp index 9bd554107..64265056b 100644 --- a/Processors/68000/Implementation/68000Implementation.hpp +++ b/Processors/68000/Implementation/68000Implementation.hpp @@ -1122,29 +1122,40 @@ template void Proces negative_flag_ = zero_result_ & 0x80000000; break; +#define sbcd() \ + /* Perform the BCD arithmetic by evaluating the two nibbles separately. */ \ + int result = (destination & 0xf) - (source & 0xf) - (extend_flag_ ? 1 : 0); \ + if(result > 0x09) result -= 0x06; \ + result += (destination & 0xf0) - (source & 0xf0); \ + if(result > 0x99) result -= 0x60; \ +\ + /* Set all flags essentially as if this were normal subtraction. */ \ + zero_result_ |= result & 0xff; \ + extend_flag_ = carry_flag_ = result & ~0xff; \ + negative_flag_ = result & 0x80; \ + overflow_flag_ = sub_overflow() & 0x80; \ +\ + /* Store the result. */ \ + active_program_->destination->halves.low.halves.low = uint8_t(result); + /* SBCD subtracts the lowest byte of the source from that of the destination using BCD arithmetic, obeying the extend flag. */ case Operation::SBCD: { - // Pull out the two halves, for simplicity. const uint8_t source = active_program_->source->halves.low.halves.low; const uint8_t destination = active_program_->destination->halves.low.halves.low; + sbcd(); + } break; - // Perform the BCD add by evaluating the two nibbles separately. - int result = (destination & 0xf) - (source & 0xf) - (extend_flag_ ? 1 : 0); - if(result > 0x09) result -= 0x06; - result += (destination & 0xf0) - (source & 0xf0); - if(result > 0x99) result -= 0x60; - - // Set all flags essentially as if this were normal subtraction. - zero_result_ |= result & 0xff; - extend_flag_ = carry_flag_ = result & ~0xff; - negative_flag_ = result & 0x80; - overflow_flag_ = sub_overflow() & 0x80; - - // Store the result. - active_program_->destination->halves.low.halves.low = uint8_t(result); + /* + NBCD is like SBCD except that the result is 0 - destination rather than + destination - source. + */ + case Operation::NBCD: { + const uint8_t source = active_program_->destination->halves.low.halves.low; + const uint8_t destination = 0; + sbcd(); } break; // EXG and SWAP exchange/swap words or long words. diff --git a/Processors/68000/Implementation/68000Storage.cpp b/Processors/68000/Implementation/68000Storage.cpp index e06f9f8a5..a33e7b3ef 100644 --- a/Processors/68000/Implementation/68000Storage.cpp +++ b/Processors/68000/Implementation/68000Storage.cpp @@ -421,7 +421,7 @@ struct ProcessorStorageConstructor { MOVE, // Maps a source mode and register and a destination mode and register to a MOVE. MOVEtoSRCCR, // Maps a source mode and register to a MOVE to SR or MOVE to CCR. - MOVEfromSR, // Maps a source mode and register to a MOVE fom SR. + MOVEfromSR_NBCD, // Maps a source mode and register to a MOVE fom SR. MOVEq, // Maps a destination register to a MOVEQ. MULU_MULS, // Maps a destination register and a source mode and register to a MULU or MULS. @@ -483,8 +483,9 @@ struct ProcessorStorageConstructor { NB: a vector is used to allow easy iteration. */ const std::vector mappings = { - {0xf1f0, 0xc100, Operation::ABCD, Decoder::ABCD_SBCD}, // 4-3 (p107) - {0xf1f0, 0x8100, Operation::SBCD, Decoder::ABCD_SBCD}, // 4-171 (p275) + {0xf1f0, 0xc100, Operation::ABCD, Decoder::ABCD_SBCD}, // 4-3 (p107) + {0xf1f0, 0x8100, Operation::SBCD, Decoder::ABCD_SBCD}, // 4-171 (p275) + {0xffc0, 0x4800, Operation::NBCD, Decoder::MOVEfromSR_NBCD}, // 4-142 (p246) {0xf0c0, 0xc000, Operation::ANDb, Decoder::AND_OR_EOR}, // 4-15 (p119) {0xf0c0, 0xc040, Operation::ANDw, Decoder::AND_OR_EOR}, // 4-15 (p119) @@ -522,9 +523,9 @@ struct ProcessorStorageConstructor { {0xf000, 0x2000, Operation::MOVEl, Decoder::MOVE}, // 4-116 (p220) {0xf000, 0x3000, Operation::MOVEw, Decoder::MOVE}, // 4-116 (p220) - {0xffc0, 0x46c0, Operation::MOVEtoSR, Decoder::MOVEtoSRCCR}, // 6-19 (p473) - {0xffc0, 0x44c0, Operation::MOVEtoCCR, Decoder::MOVEtoSRCCR}, // 4-123 (p227) - {0xffc0, 0x40c0, Operation::MOVEfromSR, Decoder::MOVEfromSR}, // 6-17 (p471) + {0xffc0, 0x46c0, Operation::MOVEtoSR, Decoder::MOVEtoSRCCR}, // 6-19 (p473) + {0xffc0, 0x44c0, Operation::MOVEtoCCR, Decoder::MOVEtoSRCCR}, // 4-123 (p227) + {0xffc0, 0x40c0, Operation::MOVEfromSR, Decoder::MOVEfromSR_NBCD}, // 6-17 (p471) {0xf1c0, 0xb000, Operation::CMPb, Decoder::CMP}, // 4-75 (p179) {0xf1c0, 0xb040, Operation::CMPw, Decoder::CMP}, // 4-75 (p179) @@ -2488,9 +2489,10 @@ struct ProcessorStorageConstructor { } } break; - case Decoder::MOVEfromSR: { + case Decoder::MOVEfromSR_NBCD: { storage_.instructions[instruction].set_destination(storage_, ea_mode, ea_register); - storage_.instructions[instruction].requires_supervisor = true; + + is_byte_access = operation == Operation::NBCD; const int mode = combined_mode(ea_mode, ea_register); switch(mode) { @@ -2500,25 +2502,18 @@ struct ProcessorStorageConstructor { op(Action::PerformOperation, seq("np n")); break; - // NOTE ON nr BELOW. - // It appears the 68000 performs a read-modify-write for this operation even - // though it doesn't use the read; therefore where it's easier I've left the - // nr within the same set of bus steps, before the PerformOperation, as it's - // then a harmless read. - // - // DO NOT CORRECT TO nrd. - case Ind: // MOVE SR, (An) case PostInc: // MOVE SR, (An)+ - op(Action::PerformOperation, seq("nr np nw", { a(ea_register), a(ea_register) })); + op(Action::None, seq("nrd", { a(ea_register) }, !is_byte_access)); + op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access)); if(mode == PostInc) { op(int(Action::Increment2) | MicroOp::DestinationMask); } break; case PreDec: // MOVE SR, -(An) - op(int(Action::Decrement2) | MicroOp::DestinationMask); - op(Action::PerformOperation, seq("n nr np nw", { a(ea_register), a(ea_register) })); + op(int(Action::Decrement2) | MicroOp::DestinationMask, seq("n nrd", { a(ea_register) }, !is_byte_access)); + op(Action::PerformOperation, seq("np nw", { a(ea_register) }, !is_byte_access)); break; case XXXl: // MOVE SR, (xxx).l @@ -2526,8 +2521,8 @@ struct ProcessorStorageConstructor { case XXXw: // MOVE SR, (xxx).w case d16An: // MOVE SR, (d16, An) case d8AnXn: // MOVE SR, (d8, An, Xn) - op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nr", mode), { ea(1) })); - op(Action::PerformOperation, seq("np nw", { ea(1) })); + op(address_action_for_mode(mode) | MicroOp::DestinationMask, seq(pseq("np nrd", mode), { ea(1) }, !is_byte_access)); + op(Action::PerformOperation, seq("np nw", { ea(1) }, !is_byte_access)); break; } } break; diff --git a/Processors/68000/Implementation/68000Storage.hpp b/Processors/68000/Implementation/68000Storage.hpp index 005ce1dba..8d3263ed9 100644 --- a/Processors/68000/Implementation/68000Storage.hpp +++ b/Processors/68000/Implementation/68000Storage.hpp @@ -44,7 +44,7 @@ class ProcessorStorage { enum class Operation { None, - ABCD, SBCD, + ABCD, SBCD, NBCD, ADDb, ADDw, ADDl, ADDQb, ADDQw, ADDQl,