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Add AddressRegisterIndirect fetches.
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Thomas Harte
parent
c6c6213460
commit
f46e7c65c5
@ -24,24 +24,35 @@ enum ExecutionState: int {
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WaitForDTACK,
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/// Perform the proper sequence to fetch a byte or word operand.
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FetchOperandbw,
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FetchOperand_bw,
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/// Perform the proper sequence to fetch a long-word operand.
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FetchOperandl,
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FetchOperand_l,
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StoreOperand,
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// Specific addressing mode fetches.
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FetchAddressRegisterIndirect,
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FetchAddressRegisterIndirectWithPostincrement,
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FetchAddressRegisterIndirectWithPredecrement,
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FetchAddressRegisterIndirectWithDisplacement,
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FetchAddressRegisterIndirectWithIndex8bitDisplacement,
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FetchProgramCounterIndirectWithDisplacement,
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FetchProgramCounterIndirectWithIndex8bitDisplacement,
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FetchAbsoluteShort,
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FetchAbsoluteLong,
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FetchImmediateData,
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FetchAddressRegisterIndirect_bw,
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FetchAddressRegisterIndirectWithPostincrement_bw,
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FetchAddressRegisterIndirectWithPredecrement_bw,
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FetchAddressRegisterIndirectWithDisplacement_bw,
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FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw,
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FetchProgramCounterIndirectWithDisplacement_bw,
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FetchProgramCounterIndirectWithIndex8bitDisplacement_bw,
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FetchAbsoluteShort_bw,
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FetchAbsoluteLong_bw,
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FetchImmediateData_bw,
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FetchAddressRegisterIndirect_l,
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FetchAddressRegisterIndirectWithPostincrement_l,
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FetchAddressRegisterIndirectWithPredecrement_l,
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FetchAddressRegisterIndirectWithDisplacement_l,
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FetchAddressRegisterIndirectWithIndex8bitDisplacement_l,
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FetchProgramCounterIndirectWithDisplacement_l,
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FetchProgramCounterIndirectWithIndex8bitDisplacement_l,
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FetchAbsoluteShort_l,
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FetchAbsoluteLong_l,
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FetchImmediateData_l,
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// Various forms of perform; each of these will
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// perform the current instruction, then do the
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@ -248,14 +259,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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#define FetchOperands(x) \
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if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::LongWord) { \
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SetupDataAccess(temporary_address_, Microcycle::Read, Microcycle::SelectWord); \
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MoveToState(FetchOperandl); \
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MoveToState(FetchOperand_l); \
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} else { \
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if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::Byte) { \
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SetupDataAccess(temporary_address_, Microcycle::Read, Microcycle::SelectByte); \
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} else { \
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SetupDataAccess(temporary_address_, Microcycle::Read, Microcycle::SelectWord); \
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} \
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MoveToState(FetchOperandbw); \
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MoveToState(FetchOperand_bw); \
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}
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switch(instruction_.operation) {
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@ -281,6 +292,8 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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#undef CASE
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// MARK: - Fetch, dispatch.
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#define MoveToNextOperand(x) \
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++next_operand_; \
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if(next_operand_ == 2) { \
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@ -289,10 +302,10 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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} \
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MoveToState(x)
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// Check the operand flags to determine whether the operand at index
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// operand_ needs to be fetched, and if so then calculate the EA and
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// do so.
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BeginState(FetchOperandbw):
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// Check the operand flags to determine whether the byte or word
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// operand at index next_operand_ needs to be fetched, and if so
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// then calculate the EA and do so.
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BeginState(FetchOperand_bw):
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// Check that this operand is meant to be fetched; if not then either:
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//
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// (i) this operand isn't used; or
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@ -308,32 +321,32 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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case Mode::AddressRegisterDirect:
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case Mode::DataRegisterDirect:
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operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
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MoveToNextOperand(FetchOperandbw);
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MoveToNextOperand(FetchOperand_bw);
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case Mode::Quick:
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operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
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MoveToNextOperand(FetchOperandbw);
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MoveToNextOperand(FetchOperand_bw);
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case Mode::AddressRegisterIndirect:
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MoveToState(FetchAddressRegisterIndirect);
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MoveToState(FetchAddressRegisterIndirect_bw);
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case Mode::AddressRegisterIndirectWithPostincrement:
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MoveToState(FetchAddressRegisterIndirectWithPostincrement);
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MoveToState(FetchAddressRegisterIndirectWithPostincrement_bw);
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case Mode::AddressRegisterIndirectWithPredecrement:
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MoveToState(FetchAddressRegisterIndirectWithPredecrement);
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MoveToState(FetchAddressRegisterIndirectWithPredecrement_bw);
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case Mode::AddressRegisterIndirectWithDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithDisplacement);
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MoveToState(FetchAddressRegisterIndirectWithDisplacement_bw);
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case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithIndex8bitDisplacement);
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MoveToState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw);
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case Mode::ProgramCounterIndirectWithDisplacement:
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MoveToState(FetchProgramCounterIndirectWithDisplacement);
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MoveToState(FetchProgramCounterIndirectWithDisplacement_bw);
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case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchProgramCounterIndirectWithIndex8bitDisplacement);
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MoveToState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw);
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case Mode::AbsoluteShort:
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MoveToState(FetchAbsoluteShort);
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MoveToState(FetchAbsoluteShort_bw);
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case Mode::AbsoluteLong:
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MoveToState(FetchAbsoluteLong);
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MoveToState(FetchAbsoluteLong_bw);
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case Mode::ImmediateData:
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MoveToState(FetchImmediateData);
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MoveToState(FetchImmediateData_bw);
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// Should be impossible to reach.
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default:
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@ -341,6 +354,71 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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}
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break;
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// As above, but for .l.
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BeginState(FetchOperand_l):
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if(!(operand_flags_ & (1 << next_operand_))) {
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state_ = perform_state_;
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continue;
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}
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switch(instruction_.mode(next_operand_)) {
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case Mode::AddressRegisterDirect:
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case Mode::DataRegisterDirect:
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operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
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MoveToNextOperand(FetchOperand_bw);
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case Mode::Quick:
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operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
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MoveToNextOperand(FetchOperand_bw);
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case Mode::AddressRegisterIndirect:
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MoveToState(FetchAddressRegisterIndirect_l);
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case Mode::AddressRegisterIndirectWithPostincrement:
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MoveToState(FetchAddressRegisterIndirectWithPostincrement_l);
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case Mode::AddressRegisterIndirectWithPredecrement:
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MoveToState(FetchAddressRegisterIndirectWithPredecrement_l);
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case Mode::AddressRegisterIndirectWithDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithDisplacement_l);
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case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l);
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case Mode::ProgramCounterIndirectWithDisplacement:
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MoveToState(FetchProgramCounterIndirectWithDisplacement_l);
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case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
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MoveToState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l);
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case Mode::AbsoluteShort:
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MoveToState(FetchAbsoluteShort_l);
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case Mode::AbsoluteLong:
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MoveToState(FetchAbsoluteLong_l);
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case Mode::ImmediateData:
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MoveToState(FetchImmediateData_l);
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// Should be impossible to reach.
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default:
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assert(false);
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}
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break;
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// MARK: - Fetch, addressing modes.
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BeginState(FetchAddressRegisterIndirect_bw):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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temporary_address_ = effective_address_[next_operand_];
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_bw);
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BeginState(FetchAddressRegisterIndirect_l):
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effective_address_[next_operand_] = registers_[8 + instruction_.reg(next_operand_)].l;
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temporary_address_ = effective_address_[next_operand_];
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Access(operand_[next_operand_].high); // nR
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temporary_address_ += 2;
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Access(operand_[next_operand_].low); // nr
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MoveToNextOperand(FetchOperand_l);
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// MARK: - Store.
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// Store operand is a lot simpler: only one operand is ever stored, and its address
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// is already known. So this can either skip straight back to ::Decode if the target
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// is a register, otherwise a single write operation can occur.
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@ -409,22 +487,30 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
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#define TODOState(x) \
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BeginState(x): [[fallthrough]];
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TODOState(FetchAddressRegisterIndirect);
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TODOState(FetchAddressRegisterIndirectWithPostincrement);
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TODOState(FetchAddressRegisterIndirectWithPredecrement);
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TODOState(FetchAddressRegisterIndirectWithDisplacement);
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TODOState(FetchAddressRegisterIndirectWithIndex8bitDisplacement);
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TODOState(FetchProgramCounterIndirectWithDisplacement);
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TODOState(FetchProgramCounterIndirectWithIndex8bitDisplacement);
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TODOState(FetchAbsoluteShort);
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TODOState(FetchAbsoluteLong);
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TODOState(FetchImmediateData);
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TODOState(FetchOperandl);
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TODOState(FetchAddressRegisterIndirectWithPostincrement_bw);
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TODOState(FetchAddressRegisterIndirectWithPredecrement_bw);
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TODOState(FetchAddressRegisterIndirectWithDisplacement_bw);
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TODOState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw);
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TODOState(FetchProgramCounterIndirectWithDisplacement_bw);
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TODOState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw);
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TODOState(FetchAbsoluteShort_bw);
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TODOState(FetchAbsoluteLong_bw);
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TODOState(FetchImmediateData_bw);
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TODOState(FetchAddressRegisterIndirectWithPostincrement_l);
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TODOState(FetchAddressRegisterIndirectWithPredecrement_l);
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TODOState(FetchAddressRegisterIndirectWithDisplacement_l);
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TODOState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l);
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TODOState(FetchProgramCounterIndirectWithDisplacement_l);
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TODOState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l);
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TODOState(FetchAbsoluteShort_l);
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TODOState(FetchAbsoluteLong_l);
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TODOState(FetchImmediateData_l);
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#undef TODOState
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default:
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printf("Unhandled state: %d\n", state_);
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printf("Unhandled state: %d; opcode is %04x\n", state_, opcode_);
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assert(false);
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}}
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