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https://github.com/TomHarte/CLK.git
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Attempt full write loop.
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@@ -73,7 +73,7 @@ void Controller::process_write_completed() {
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// MARK: - PLL control and delegate
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void Controller::set_expected_bit_length(Time bit_length) {
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void Controller::set_expected_bit_length(const Time bit_length) {
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bit_length_ = bit_length;
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bit_length_.simplify();
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@@ -86,6 +86,10 @@ void Controller::set_expected_bit_length(Time bit_length) {
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pll_.set_clocks_per_bit(clocks_per_bit);
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}
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Storage::Time Controller::expected_bit_length() {
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return bit_length_;
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}
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void Controller::digital_phase_locked_loop_output_bit(int value) {
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if(is_reading_) process_input_bit(value);
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}
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