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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-24 05:18:36 +00:00

Attempt full write loop.

This commit is contained in:
Thomas Harte
2025-11-18 17:03:22 -05:00
parent 9e39be282b
commit f513edc006
7 changed files with 62 additions and 15 deletions
+5 -1
View File
@@ -73,7 +73,7 @@ void Controller::process_write_completed() {
// MARK: - PLL control and delegate
void Controller::set_expected_bit_length(Time bit_length) {
void Controller::set_expected_bit_length(const Time bit_length) {
bit_length_ = bit_length;
bit_length_.simplify();
@@ -86,6 +86,10 @@ void Controller::set_expected_bit_length(Time bit_length) {
pll_.set_clocks_per_bit(clocks_per_bit);
}
Storage::Time Controller::expected_bit_length() {
return bit_length_;
}
void Controller::digital_phase_locked_loop_output_bit(int value) {
if(is_reading_) process_input_bit(value);
}