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Change RTE and RTR read order.

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This commit is contained in:
Thomas Harte 2022-06-09 21:47:28 -04:00
parent dd5c903fd6
commit f8643a62e6
1 changed files with 17 additions and 8 deletions
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25
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
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@ -2396,18 +2396,25 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
Prefetch();
MoveToStateSpecific(Decode);
// Yacht cites the bus activity for RTE and RTR as nS ns ns, so
// the program counter high word must be the first thing
// retrieved; the order of the other two is a guess,
// being the converse of the write order.
BeginState(RTE):
SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
SetDataAddress(registers_[15].l);
registers_[15].l += 2;
Access(program_counter_.high);
registers_[15].l += 2;
Access(program_counter_.low);
registers_[15].l -= 4;
registers_[15].l -= 2;
Access(temporary_value_.low);
registers_[15].l += 6;
registers_[15].l += 4;
Access(program_counter_.low);
registers_[15].l += 2;
status_.set_status(temporary_value_.w);
did_update_status();
@ -2421,12 +2428,14 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
registers_[15].l += 2;
Access(program_counter_.high);
registers_[15].l += 2;
Access(program_counter_.low);
registers_[15].l -= 4;
registers_[15].l -= 2;
Access(temporary_value_.low);
registers_[15].l += 6;
registers_[15].l += 4;
Access(program_counter_.low);
registers_[15].l += 2;
status_.set_ccr(temporary_value_.w);
Prefetch();