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This commit is contained in:
Thomas Harte 2019-07-17 15:09:26 -04:00
parent 77333ff9f7
commit fa226bb1b9
2 changed files with 10 additions and 9 deletions
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12
Processors/68000/Implementation/68000Storage.hpp
View File

@ -194,12 +194,12 @@ class ProcessorStorage {
} action = Action::None;
inline bool operator ==(const BusStep &rhs) const {
forceinline bool operator ==(const BusStep &rhs) const {
if(action != rhs.action) return false;
return microcycle == rhs.microcycle;
}
inline bool is_terminal() const {
forceinline bool is_terminal() const {
return action == Action::ScheduleNextProgram;
}
};
@ -325,7 +325,7 @@ class ProcessorStorage {
MicroOp(Action action) : MicroOp(int(action)) {}
MicroOp(Action action, BusStep *bus_program) : MicroOp(int(action), bus_program) {}
inline bool is_terminal() const {
forceinline bool is_terminal() const {
return bus_program == nullptr;
}
};
@ -416,7 +416,7 @@ class ProcessorStorage {
Evaluates the conditional described by @c code and returns @c true or @c false to
indicate the result of that evaluation.
*/
inline bool evaluate_condition(uint8_t code) {
forceinline bool evaluate_condition(uint8_t code) {
switch(code & 0xf) {
default:
case 0x00: return true; // true
@ -447,7 +447,7 @@ class ProcessorStorage {
representing a short-form exception — and mutates the status register as if one
were beginning.
*/
inline void populate_trap_steps(uint32_t vector, uint16_t status) {
forceinline void populate_trap_steps(uint32_t vector, uint16_t status) {
// Fill in the status word value.
destination_bus_data_[0].full = status;
@ -468,7 +468,7 @@ class ProcessorStorage {
trap_steps_->microcycle.length = HalfCycles(8);
}
inline void populate_bus_error_steps(uint32_t vector, uint16_t status, uint16_t bus_status, RegisterPair32 faulting_address) {
forceinline void populate_bus_error_steps(uint32_t vector, uint16_t status, uint16_t bus_status, RegisterPair32 faulting_address) {
// Fill in the status word value.
destination_bus_data_[0].halves.low.full = status;
destination_bus_data_[0].halves.high.full = bus_status;

7
Processors/Z80/Z80.hpp
View File

@ -15,6 +15,7 @@
#include "../RegisterSizes.hpp"
#include "../../ClockReceiver/ClockReceiver.hpp"
#include "../../ClockReceiver/ForceInline.hpp"
namespace CPU {
namespace Z80 {
@ -107,20 +108,20 @@ struct PartialMachineCycle {
@returns @c true if the processor believes that the bus handler should actually do something with
the content of this PartialMachineCycle; @c false otherwise.
*/
inline bool expects_action() const {
forceinline bool expects_action() const {
return operation <= Operation::Interrupt;
}
/*!
@returns @c true if this partial machine cycle completes one of the documented full machine cycles;
@c false otherwise.
*/
inline bool is_terminal() const {
forceinline bool is_terminal() const {
return operation <= Operation::BusAcknowledge;
}
/*!
@returns @c true if this partial machine cycle is a wait cycle; @c false otherwise.
*/
inline bool is_wait() const {
forceinline bool is_wait() const {
return operation >= Operation::ReadOpcodeWait && operation <= Operation::InterruptWait;
}