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Ensure MOVE from SR has an effective address to write to.

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This commit is contained in:
Thomas Harte 2022-05-22 20:52:00 -04:00
parent 7d1f1a3175
commit faef5633f8
2 changed files with 21 additions and 8 deletions
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4
OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
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@ -182,7 +182,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
// @"moveq.json", // @"moveq.json",
@"mulu_muls.json", @"mulu_muls.json",
@"nbcd_pea.json", @"nbcd_pea.json",
// @"neg_not.json", @"neg_not.json",
// @"negx_clr.json", // @"negx_clr.json",
// @"rtr.json", // @"rtr.json",
// @"rts.json", // @"rts.json",
@ -190,7 +190,7 @@ struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
@"tas.json", @"tas.json",
@"tst.json", @"tst.json",
]]; ]];
_testSet = [NSSet setWithArray:@[@"MOVE to CCR 44d3"]]; // _testSet = [NSSet setWithArray:@[@"MOVE from SR 40eb"]];
} }
- (void)testAll { - (void)testAll {

25
Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
View File

@ -735,10 +735,11 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
StdCASE(MOVEfromSR, { StdCASE(MOVEfromSR, {
if(instruction_.mode(0) == Mode::DataRegisterDirect) { if(instruction_.mode(0) == Mode::DataRegisterDirect) {
perform_state_ = Perform_np_n; post_ea_state_ = Perform_np_n;
} else { } else {
perform_state_ = Perform_np; post_ea_state_ = Perform_np;
} }
MoveToStateSpecific(CalcEffectiveAddress);
}); });
default: default:
@ -855,8 +856,7 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
BeginState(CalcEffectiveAddress): BeginState(CalcEffectiveAddress):
switch(instruction_.mode(next_operand_)) { switch(instruction_.mode(next_operand_)) {
default: default:
assert(false); MoveToStateDynamic(post_ea_state_);
break;
case Mode::AddressRegisterIndirect: case Mode::AddressRegisterIndirect:
MoveToStateSpecific(CalcAddressRegisterIndirect); MoveToStateSpecific(CalcAddressRegisterIndirect);
@ -1242,9 +1242,22 @@ void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perfor
MoveToNextOperand(StoreOperand_bw); MoveToNextOperand(StoreOperand_bw);
} }
if(instruction_.mode(next_operand_) <= Mode::AddressRegisterDirect) { // Assumption enshrined here: there are no write-only Dn
registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_]; // byte operations. i.e. anything that should technically
// write back only a byte will have read from the register
// before the operation, making it safe to write back the
// entire word.
//
// However there are write-only Dn word operations, and
// the sign-extended top half needs to be kept for An.
switch(instruction_.mode(next_operand_)) {
case Mode::DataRegisterDirect:
registers_[instruction_.lreg(next_operand_)].w = operand_[next_operand_].w;
MoveToNextOperand(StoreOperand_bw); MoveToNextOperand(StoreOperand_bw);
case Mode::AddressRegisterDirect:
registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
MoveToNextOperand(StoreOperand_bw);
default: break;
} }
SetDataAddress(effective_address_[next_operand_].l); SetDataAddress(effective_address_[next_operand_].l);