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Improves resizeable microcycle test.

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This commit is contained in:
Thomas Harte 2019-06-24 10:55:22 -04:00
parent d27ba90c07
commit faef917cbd
5 changed files with 9 additions and 15 deletions
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2
OSBindings/Mac/Clock SignalTests/68000Tests.mm
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@ -1189,7 +1189,7 @@ class CPU::MC68000::ProcessorStorageTests {
const auto state = _machine->get_processor_state();
XCTAssertEqual(state.data[1], 1);
XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
// XCTAssertEqual(158, _machine->get_cycle_count());
XCTAssertEqual(158, _machine->get_cycle_count());
}
- (void)testDIVS_4 {

4
Processors/68000/68000.hpp
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@ -189,6 +189,10 @@ struct Microcycle {
uint32_t word_address() const {
return (address ? (*address) & 0x00fffffe : 0) >> 1;
}
#ifndef NDEBUG
bool is_resizeable = false;
#endif
};
/*!

4
Processors/68000/Implementation/68000Implementation.hpp
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@ -52,7 +52,7 @@
// Sets the length of the next microcycle; if this is a debug build, also confirms
// that the microcycle being adjusted is the one that it's permissible to adjust.
#define set_next_microcycle_length(x) \
assert(resizeable_microcycle_ == &bus_program->microcycle); \
assert(bus_program->microcycle.is_resizeable); \
bus_program->microcycle.length = x
template <class T, bool dtack_is_implicit, bool signal_will_perform> void Processor<T, dtack_is_implicit, signal_will_perform>::run_for(HalfCycles duration) {
@ -948,7 +948,7 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
bus_program = active_micro_op_->bus_program; \
\
populate_trap_steps(5, get_status()); \
set_next_microcycle_length(HalfCycles(8)); \
bus_program->microcycle.length = HalfCycles(8); \
\
program_counter_.full -= 2;

9
Processors/68000/Implementation/68000Storage.cpp
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@ -3048,13 +3048,8 @@ struct ProcessorStorageConstructor {
// If this is a debug build, not where the resizeable microcycle is
// (and double check that there's only the one).
#ifndef NDEBUG
for(size_t c = 0; c < storage_.all_bus_steps_.size() - 1; ++c) {
if(!storage_.all_bus_steps_[c+1].is_terminal()) continue;
if(storage_.all_bus_steps_[c].microcycle.length == HalfCycles(0)) {
assert(!storage_.resizeable_microcycle_);
storage_.resizeable_microcycle_ = &storage_.all_bus_steps_[c].microcycle;
}
for(auto &bus_step: storage_.all_bus_steps_) {
bus_step.microcycle.is_resizeable = bus_step.microcycle.length == HalfCycles(0);
}
#endif

5
Processors/68000/Implementation/68000Storage.hpp
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@ -411,11 +411,6 @@ class ProcessorStorage {
RegisterPair16 throwaway_value_;
uint32_t movem_final_address_;
// Sanity checking for the debug build.
#ifndef NDEBUG
const Microcycle *resizeable_microcycle_ = nullptr;
#endif
/*!
Evaluates the conditional described by @c code and returns @c true or @c false to
indicate the result of that evaluation.