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Merge pull request #1045 from TomHarte/InAmiga

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Switch the Amiga to the newer 68000.
This commit is contained in:
Thomas Harte
2022-06-30 17:14:54 -04:00
committed by GitHub
parent c85ca09236 6a2d4ae11d
commit fca974723f
4 changed files with 14 additions and 14 deletions
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12
Machines/Amiga/Amiga.cpp
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@@ -11,7 +11,7 @@
#include "../../Activity/Source.hpp" #include "../../Activity/Source.hpp"
#include "../MachineTypes.hpp" #include "../MachineTypes.hpp"
#include "../../Processors/68000/68000.hpp" #include "../../Processors/68000Mk2/68000Mk2.hpp"
#include "../../Analyser/Static/Amiga/Target.hpp" #include "../../Analyser/Static/Amiga/Target.hpp"
@@ -41,7 +41,7 @@ namespace Amiga {
class ConcreteMachine: class ConcreteMachine:
public Activity::Source, public Activity::Source,
public CPU::MC68000::BusHandler, public CPU::MC68000Mk2::BusHandler,
public MachineTypes::AudioProducer, public MachineTypes::AudioProducer,
public MachineTypes::JoystickMachine, public MachineTypes::JoystickMachine,
public MachineTypes::MappedKeyboardMachine, public MachineTypes::MappedKeyboardMachine,
@@ -80,8 +80,7 @@ class ConcreteMachine:
} }
// MARK: - MC68000::BusHandler. // MARK: - MC68000::BusHandler.
using Microcycle = CPU::MC68000::Microcycle; template <typename Microcycle> HalfCycles perform_bus_operation(const Microcycle &cycle, int) {
HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
// Do a quick advance check for Chip RAM access; add a suitable delay if required. // Do a quick advance check for Chip RAM access; add a suitable delay if required.
HalfCycles total_length; HalfCycles total_length;
@@ -97,7 +96,7 @@ class ConcreteMachine:
// Check for assertion of reset. // Check for assertion of reset.
if(cycle.operation & Microcycle::Reset) { if(cycle.operation & Microcycle::Reset) {
memory_.reset(); memory_.reset();
LOG("Reset; PC is around " << PADHEX(8) << mc68000_.get_state().program_counter); LOG("Reset; PC is around " << PADHEX(8) << mc68000_.get_state().registers.program_counter);
} }
// Autovector interrupts. // Autovector interrupts.
@@ -182,7 +181,7 @@ class ConcreteMachine:
} }
private: private:
CPU::MC68000::Processor<ConcreteMachine, true> mc68000_; CPU::MC68000Mk2::Processor<ConcreteMachine, true, true> mc68000_;
// MARK: - Memory map. // MARK: - Memory map.
@@ -218,6 +217,7 @@ class ConcreteMachine:
void run_for(const Cycles cycles) { void run_for(const Cycles cycles) {
mc68000_.run_for(cycles); mc68000_.run_for(cycles);
flush();
} }
// MARK: - MachineTypes::MouseMachine. // MARK: - MachineTypes::MouseMachine.

4
Machines/Amiga/Chipset.cpp
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@@ -817,8 +817,8 @@ void Chipset::update_interrupts() {
} }
} }
void Chipset::perform(const CPU::MC68000::Microcycle &cycle) { void Chipset::perform(const CPU::MC68000Mk2::Microcycle &cycle) {
using Microcycle = CPU::MC68000::Microcycle; using Microcycle = CPU::MC68000Mk2::Microcycle;
const uint32_t register_address = *cycle.address & ChipsetAddressMask; const uint32_t register_address = *cycle.address & ChipsetAddressMask;
if(cycle.operation & Microcycle::Read) { if(cycle.operation & Microcycle::Read) {

4
Machines/Amiga/Chipset.hpp
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@@ -20,7 +20,7 @@
#include "../../ClockReceiver/JustInTime.hpp" #include "../../ClockReceiver/JustInTime.hpp"
#include "../../Components/6526/6526.hpp" #include "../../Components/6526/6526.hpp"
#include "../../Outputs/CRT/CRT.hpp" #include "../../Outputs/CRT/CRT.hpp"
#include "../../Processors/68000/68000.hpp" #include "../../Processors/68000Mk2/68000Mk2.hpp"
#include "../../Storage/Disk/Controller/DiskController.hpp" #include "../../Storage/Disk/Controller/DiskController.hpp"
#include "../../Storage/Disk/Drive.hpp" #include "../../Storage/Disk/Drive.hpp"
@@ -58,7 +58,7 @@ class Chipset: private ClockingHint::Observer {
Changes run_until_after_cpu_slot(); Changes run_until_after_cpu_slot();
/// Performs the provided microcycle, which the caller guarantees to be a memory access. /// Performs the provided microcycle, which the caller guarantees to be a memory access.
void perform(const CPU::MC68000::Microcycle &); void perform(const CPU::MC68000Mk2::Microcycle &);
/// Sets the current state of the CIA interrupt lines. /// Sets the current state of the CIA interrupt lines.
void set_cia_interrupts(bool cia_a, bool cia_b); void set_cia_interrupts(bool cia_a, bool cia_b);

8
Machines/Amiga/MemoryMap.hpp
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@@ -19,8 +19,8 @@ namespace Amiga {
class MemoryMap { class MemoryMap {
private: private:
static constexpr auto PermitRead = CPU::MC68000::Microcycle::PermitRead; static constexpr auto PermitRead = CPU::MC68000Mk2::Microcycle::PermitRead;
static constexpr auto PermitWrite = CPU::MC68000::Microcycle::PermitWrite; static constexpr auto PermitWrite = CPU::MC68000Mk2::Microcycle::PermitWrite;
static constexpr auto PermitReadWrite = PermitRead | PermitWrite; static constexpr auto PermitReadWrite = PermitRead | PermitWrite;
public: public:
@@ -109,12 +109,12 @@ class MemoryMap {
/// Performs the provided microcycle, which the caller guarantees to be a memory access, /// Performs the provided microcycle, which the caller guarantees to be a memory access,
/// and in the Zorro register range. /// and in the Zorro register range.
bool perform(const CPU::MC68000::Microcycle &cycle) { bool perform(const CPU::MC68000Mk2::Microcycle &cycle) {
if(!fast_autoconf_visible_) return false; if(!fast_autoconf_visible_) return false;
const uint32_t register_address = *cycle.address & 0xfe; const uint32_t register_address = *cycle.address & 0xfe;
using Microcycle = CPU::MC68000::Microcycle; using Microcycle = CPU::MC68000Mk2::Microcycle;
if(cycle.operation & Microcycle::Read) { if(cycle.operation & Microcycle::Read) {
// Re: Autoconf: // Re: Autoconf:
// //