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https://github.com/TomHarte/CLK.git
synced 2024-09-05 13:29:06 +00:00
Starts to formalise the ST memory map a little.
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@ -45,6 +45,17 @@ class ConcreteMachine:
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throw ROMMachine::Error::MissingROMs;
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throw ROMMachine::Error::MissingROMs;
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}
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}
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Memory::PackBigEndian16(*roms[0], rom_);
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Memory::PackBigEndian16(*roms[0], rom_);
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// Set up basic memory map.
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memory_map_[0] = BusDevice::MostlyRAM;
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for(int c = 1; c < 0xf0; ++c) memory_map_[c] = BusDevice::RAM;
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// This is appropriate for: TOS 1.x, no cartridge.
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for(int c = 0xf0; c < 0xfc; ++c) memory_map_[c] = BusDevice::Unassigned;
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for(int c = 0xfc; c < 0xff; ++c) memory_map_[c] = BusDevice::ROM;
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memory_map_[0xfa] = memory_map_[0xfb] = BusDevice::Cartridge;
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memory_map_[0xff] = BusDevice::IO;
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}
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}
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// MARK: CRTMachine::Machine
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// MARK: CRTMachine::Machine
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@ -69,22 +80,49 @@ class ConcreteMachine:
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// A null cycle leaves nothing else to do.
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// A null cycle leaves nothing else to do.
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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if(!(cycle.operation & (Microcycle::NewAddress | Microcycle::SameAddress))) return HalfCycles(0);
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/* TODO: DTack, bus error, VPA. */
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auto address = cycle.word_address();
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auto address = cycle.word_address();
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uint16_t *memory;
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uint16_t *memory;
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if(address < 4) {
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switch(memory_map_[address >> 15]) {
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memory = rom_.data();
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case BusDevice::MostlyRAM:
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} else if(address < 0x700000) {
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if(address < 4) {
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memory = ram_.data();
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memory = rom_.data();
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address &= ram_.size() - 1;
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break;
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// TODO: align with the next access window.
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}
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} else if(address < 0x780000) { // TOS 2.0+ address
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case BusDevice::RAM:
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memory = rom_.data();
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memory = ram_.data();
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address &= rom_.size() - 1;
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address &= ram_.size() - 1;
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} else if(address >= 0x7e0000 && address < 0x7f8000) { // TOS 1.0 address
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// TODO: align with the next access window.
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memory = rom_.data();
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break;
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address &= rom_.size() - 1;
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} else {
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case BusDevice::ROM:
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assert(false);
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memory = rom_.data();
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address %= rom_.size();
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break;
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case BusDevice::Cartridge:
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/*
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TOS 1.0 appears to attempt to read from the catridge before it has setup
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the bus error vector. Therefore I assume no bus error flows.
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*/
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switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
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default: break;
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case Microcycle::SelectWord | Microcycle::Read:
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*cycle.value = 0xffff;
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break;
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case Microcycle::SelectByte | Microcycle::Read:
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cycle.value->halves.low = 0xff;
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break;
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}
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return HalfCycles(0);
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case BusDevice::Unassigned:
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return HalfCycles(0);
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case BusDevice::IO:
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assert(false);
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break;
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}
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}
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
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@ -119,6 +157,10 @@ class ConcreteMachine:
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std::vector<uint16_t> ram_;
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std::vector<uint16_t> ram_;
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std::vector<uint16_t> rom_;
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std::vector<uint16_t> rom_;
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enum class BusDevice {
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MostlyRAM, RAM, ROM, Cartridge, IO, Unassigned
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};
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BusDevice memory_map_[256];
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};
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};
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}
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}
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