mirror of
https://github.com/TomHarte/CLK.git
synced 2024-07-07 08:28:57 +00:00
Merge pull request #640 from TomHarte/InterruptSignalling
Corrects 68000 address lines during interrupt acknowledgement.
This commit is contained in:
commit
fd2fbe0e59
@ -180,7 +180,12 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
|
|||||||
// All code below deals only with reads and writes — cycles in which a
|
// All code below deals only with reads and writes — cycles in which a
|
||||||
// data select is active. So quit now if this is not the active part of
|
// data select is active. So quit now if this is not the active part of
|
||||||
// a read or write.
|
// a read or write.
|
||||||
if(!cycle.data_select_active()) return delay;
|
//
|
||||||
|
// The 68000 uses 6800-style autovectored interrupts, so the mere act of
|
||||||
|
// having set VPA above deals with those given that the generated address
|
||||||
|
// for interrupt acknowledge cycles always has all bits set except the
|
||||||
|
// lowest explicit address lines.
|
||||||
|
if(!cycle.data_select_active() || (cycle.operation & Microcycle::InterruptAcknowledge)) return delay;
|
||||||
|
|
||||||
uint16_t *memory_base = nullptr;
|
uint16_t *memory_base = nullptr;
|
||||||
switch(memory_map_[word_address >> 18]) {
|
switch(memory_map_[word_address >> 18]) {
|
||||||
@ -294,17 +299,10 @@ template <Analyser::Static::Macintosh::Target::Model model> class ConcreteMachin
|
|||||||
}
|
}
|
||||||
|
|
||||||
// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
|
// If control has fallen through to here, the access is either a read from ROM, or a read or write to RAM.
|
||||||
// TODO: interrupt acknowledge cycles also end up here, which may suggest the 68000 is loading the address bus
|
switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
|
||||||
// incorrectly during interrupt acknowledgment cycles. Check.
|
|
||||||
switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read | Microcycle::InterruptAcknowledge)) {
|
|
||||||
default:
|
default:
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case Microcycle::InterruptAcknowledge | Microcycle::SelectByte:
|
|
||||||
// The Macintosh uses autovectored interrupts.
|
|
||||||
mc68000_.set_is_peripheral_address(true);
|
|
||||||
break;
|
|
||||||
|
|
||||||
case Microcycle::SelectWord | Microcycle::Read:
|
case Microcycle::SelectWord | Microcycle::Read:
|
||||||
cycle.value->full = memory_base[word_address];
|
cycle.value->full = memory_base[word_address];
|
||||||
break;
|
break;
|
||||||
|
@ -234,12 +234,6 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
|
|||||||
continue;
|
continue;
|
||||||
|
|
||||||
case ExecutionState::BeginInterrupt:
|
case ExecutionState::BeginInterrupt:
|
||||||
#ifdef LOG_TRACE
|
|
||||||
// should_log = true;
|
|
||||||
if(should_log) {
|
|
||||||
printf("\n\nInterrupt\n\n");
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
active_program_ = nullptr;
|
active_program_ = nullptr;
|
||||||
active_micro_op_ = interrupt_micro_ops_;
|
active_micro_op_ = interrupt_micro_ops_;
|
||||||
execution_state_ = ExecutionState::Executing;
|
execution_state_ = ExecutionState::Executing;
|
||||||
@ -1960,10 +1954,12 @@ template <class T, bool dtack_is_implicit, bool signal_will_perform> void Proces
|
|||||||
|
|
||||||
// Mutate neessary internal state — effective_address_[0] is exposed
|
// Mutate neessary internal state — effective_address_[0] is exposed
|
||||||
// on the data bus as the accepted interrupt number during the interrupt
|
// on the data bus as the accepted interrupt number during the interrupt
|
||||||
// acknowledge cycle, with the low bit set since a real 68000 uses the lower
|
// acknowledge cycle, with all other bits set, including the low bit as
|
||||||
// data strobe to collect the corresponding vector byte.
|
// a real 68000 uses the lower data strobe to collect the corresponding vector byte.
|
||||||
|
//
|
||||||
|
// Cf. M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL 5.1.4.
|
||||||
accepted_interrupt_level_ = interrupt_level_ = bus_interrupt_level_;
|
accepted_interrupt_level_ = interrupt_level_ = bus_interrupt_level_;
|
||||||
effective_address_[0].full = 1 | uint32_t(accepted_interrupt_level_ << 1);
|
effective_address_[0].full = 0xfffffff1 | uint32_t(accepted_interrupt_level_ << 1);
|
||||||
|
|
||||||
// Recede the program counter to where it would have been were there no
|
// Recede the program counter to where it would have been were there no
|
||||||
// prefetch; that's where the reading stream should pick up upon RTE.
|
// prefetch; that's where the reading stream should pick up upon RTE.
|
||||||
|
Loading…
Reference in New Issue
Block a user