diff --git a/InstructionSets/M68k/ExceptionVectors.hpp b/InstructionSets/M68k/ExceptionVectors.hpp
index 83fbf2552..e56c71efb 100644
--- a/InstructionSets/M68k/ExceptionVectors.hpp
+++ b/InstructionSets/M68k/ExceptionVectors.hpp
@@ -29,7 +29,7 @@ enum Exception {
 	FormatError							= 14,
 	UninitialisedInterrupt				= 15,
 	SpuriousInterrupt					= 24,
-	InterruptAutovectorBase				= 25,
+	InterruptAutovectorBase				= 25,	// This is the vector for interrupt level _1_.
 	TrapBase							= 32,
 	FPBranchOrSetOnUnorderedCondition	= 48,
 	FPInexactResult						= 49,
diff --git a/InstructionSets/M68k/Executor.hpp b/InstructionSets/M68k/Executor.hpp
index 35009461f..0fe9ef3a6 100644
--- a/InstructionSets/M68k/Executor.hpp
+++ b/InstructionSets/M68k/Executor.hpp
@@ -13,6 +13,7 @@
 #include "Instruction.hpp"
 #include "Model.hpp"
 #include "Perform.hpp"
+#include "RegisterSet.hpp"
 #include "Status.hpp"
 
 namespace InstructionSet {
@@ -80,17 +81,9 @@ template <Model model, typename BusHandler> class Executor {
 		/// Sets the current input interrupt level.
 		void set_interrupt_level(int);
 
-		// TODO: this will likely be shared in some capacity with the bus-accurate versions of the 680x0;
-		// therefore it will almost certainly be factored out in future.
-		struct Registers {
-			uint32_t data[8], address[7];
-			uint32_t user_stack_pointer;
-			uint32_t supervisor_stack_pointer;
-			uint16_t status;
-			uint32_t program_counter;
-		};
-		Registers get_state();
-		void set_state(const Registers &);
+		// State for the executor is just the register set.
+		RegisterSet get_state();
+		void set_state(const RegisterSet &);
 
 	private:
 		class State: public NullFlowController {
diff --git a/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp b/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp
index 682c4507b..1d129a354 100644
--- a/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp
+++ b/InstructionSets/M68k/Implementation/ExecutorImplementation.hpp
@@ -53,7 +53,7 @@ void Executor<model, BusHandler>::signal_bus_error(FunctionCode code, uint32_t a
 template <Model model, typename BusHandler>
 void Executor<model, BusHandler>::set_interrupt_level(int level) {
 	state_.interrupt_input_ = level;
-	state_.stopped &= state_.interrupt_input_ <= state_.status.interrupt_level;
+	state_.stopped &= !state_.status.would_accept_interrupt(level);
 }
 
 template <Model model, typename BusHandler>
@@ -102,8 +102,8 @@ void Executor<model, BusHandler>::run_for_instructions(int count) {
 }
 
 template <Model model, typename BusHandler>
-typename Executor<model, BusHandler>::Registers Executor<model, BusHandler>::get_state() {
-	Registers result;
+RegisterSet Executor<model, BusHandler>::get_state() {
+	RegisterSet result;
 
 	for(int c = 0; c < 8; c++) {
 		result.data[c] = Dn(c).l;
@@ -122,7 +122,7 @@ typename Executor<model, BusHandler>::Registers Executor<model, BusHandler>::get
 }
 
 template <Model model, typename BusHandler>
-void Executor<model, BusHandler>::set_state(const Registers &state) {
+void Executor<model, BusHandler>::set_state(const RegisterSet &state) {
 	for(int c = 0; c < 8; c++) {
 		Dn(c).l = state.data[c];
 	}
@@ -205,8 +205,8 @@ uint32_t Executor<model, BusHandler>::State::index_8bitdisplacement() {
 	// also include the scale field even if not.
 	const auto extension = read_pc<uint16_t>();
 	const auto offset = int8_t(extension);
-	const int register_index = (extension >> 12) & 7;
-	const uint32_t displacement = registers[register_index + ((extension >> 12) & 0x08)].l;
+	const int register_index = (extension >> 12) & 15;
+	const uint32_t displacement = registers[register_index].l;
 	const uint32_t sized_displacement = (extension & 0x800) ? displacement : int16_t(displacement);
 	return offset + sized_displacement;
 }
@@ -324,7 +324,7 @@ template <Model model, typename BusHandler>
 void Executor<model, BusHandler>::State::run(int &count) {
 	while(count--) {
 		// Check for a new interrupt.
-		if(interrupt_input > status.interrupt_level) {
+		if(status.would_accept_interrupt(interrupt_input)) {
 			const int vector = bus_handler_.acknowlege_interrupt(interrupt_input);
 			if(vector >= 0) {
 				raise_exception<false>(vector);
@@ -483,7 +483,7 @@ template <Model model, typename BusHandler>
 void Executor<model, BusHandler>::State::bsr(uint32_t offset) {
 	sp.l -= 4;
 	write<uint32_t>(sp.l, program_counter.l);
-	program_counter.l = instruction_address + offset;
+	program_counter.l = instruction_address + offset + 2;
 }
 
 template <Model model, typename BusHandler>
diff --git a/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp b/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
index 2d42cafd0..ca29cc574 100644
--- a/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
+++ b/InstructionSets/M68k/Implementation/InstructionOperandFlags.hpp
@@ -12,7 +12,7 @@
 namespace InstructionSet {
 namespace M68k {
 
-template <Model model, Operation t_operation> uint8_t operand_flags(Operation r_operation) {
+template <Model model, Operation t_operation> constexpr uint8_t operand_flags(Operation r_operation) {
 	switch((t_operation != Operation::Undefined) ? t_operation : r_operation) {
 		default:
 			assert(false);
@@ -24,8 +24,6 @@ template <Model model, Operation t_operation> uint8_t operand_flags(Operation r_
 		case Operation::PEA:
 		case Operation::JMP:		case Operation::JSR:
 		case Operation::MOVEPw:		case Operation::MOVEPl:
-		case Operation::MOVEMtoMw:	case Operation::MOVEMtoMl:
-		case Operation::MOVEMtoRw:	case Operation::MOVEMtoRl:
 		case Operation::TAS:
 		case Operation::RTR:		case Operation::RTS:		case Operation::RTE:
 			return 0;
@@ -40,13 +38,14 @@ template <Model model, Operation t_operation> uint8_t operand_flags(Operation r_
 		case Operation::Bccb:		case Operation::Bccw:		case Operation::Bccl:
 		case Operation::BSRb:		case Operation::BSRw:		case Operation::BSRl:
 		case Operation::TSTb:		case Operation::TSTw:		case Operation::TSTl:
+		case Operation::MOVEMtoMw:	case Operation::MOVEMtoMl:
+		case Operation::MOVEMtoRw:	case Operation::MOVEMtoRl:
 			return FetchOp1;
 
 		//
 		//	Single-operand write.
 		//
-		case Operation::MOVEfromSR:	case Operation::MOVEfromUSP:
-		case Operation::Scc:
+		case Operation::MOVEfromUSP:
 			return StoreOp1;
 
 		//
@@ -63,11 +62,13 @@ template <Model model, Operation t_operation> uint8_t operand_flags(Operation r_
 		case Operation::LSLm:		case Operation::LSRm:
 		case Operation::ROLm:		case Operation::RORm:
 		case Operation::ROXLm:		case Operation::ROXRm:
+		case Operation::Scc:
 			return FetchOp1 | StoreOp1;
 
 		//
-		//	CLR, which is model-dependent.
+		//	CLR and MOVE SR, which are model-dependent.
 		//
+		case Operation::MOVEfromSR:
 		case Operation::CLRb:	case Operation::CLRw:	case Operation::CLRl:
 			if constexpr (model == Model::M68000) {
 				return FetchOp1 | StoreOp1;
diff --git a/InstructionSets/M68k/Implementation/InstructionOperandSize.hpp b/InstructionSets/M68k/Implementation/InstructionOperandSize.hpp
index 7c00c26de..67242e522 100644
--- a/InstructionSets/M68k/Implementation/InstructionOperandSize.hpp
+++ b/InstructionSets/M68k/Implementation/InstructionOperandSize.hpp
@@ -12,8 +12,9 @@
 namespace InstructionSet {
 namespace M68k {
 
-constexpr DataSize operand_size(Operation operation) {
-	switch(operation) {
+template <Operation t_operation>
+constexpr DataSize operand_size(Operation r_operation) {
+	switch((t_operation == Operation::Undefined) ? r_operation : t_operation) {
 		// These are given a value arbitrarily, to
 		// complete the switch statement.
 		case Operation::Undefined:
diff --git a/InstructionSets/M68k/Implementation/PerformImplementation.hpp b/InstructionSets/M68k/Implementation/PerformImplementation.hpp
index 909734cea..66af70912 100644
--- a/InstructionSets/M68k/Implementation/PerformImplementation.hpp
+++ b/InstructionSets/M68k/Implementation/PerformImplementation.hpp
@@ -228,7 +228,7 @@ template <
 
 			status.zero_result = dest.l & bit_mask;
 			dest.l &= ~bit_mask;
-			flow_controller.did_bit_op(bit_position);
+			flow_controller.did_bit_op(int(bit_position));
 		} break;
 
 		case Operation::BCHG: {
@@ -236,7 +236,7 @@ template <
 
 			status.zero_result = dest.l & bit_mask;
 			dest.l ^= bit_mask;
-			flow_controller.did_bit_op(bit_position);
+			flow_controller.did_bit_op(int(bit_position));
 		} break;
 
 		case Operation::BSET: {
@@ -244,7 +244,7 @@ template <
 
 			status.zero_result = dest.l & bit_mask;
 			dest.l |= bit_mask;
-			flow_controller.did_bit_op(bit_position);
+			flow_controller.did_bit_op(int(bit_position));
 		} break;
 
 #undef get_mask
@@ -252,29 +252,29 @@ template <
 		case Operation::Bccb:
 			flow_controller.template complete_bcc<int8_t>(
 				status.evaluate_condition(instruction.condition()),
-				src.b);
+				int8_t(src.b));
 		break;
 
 		case Operation::Bccw:
 			flow_controller.template complete_bcc<int16_t>(
 				status.evaluate_condition(instruction.condition()),
-				src.w);
+				int16_t(src.w));
 		break;
 
 		case Operation::Bccl:
 			flow_controller.template complete_bcc<int32_t>(
 				status.evaluate_condition(instruction.condition()),
-				src.l);
+				int32_t(src.l));
 		break;
 
 		case Operation::BSRb:
-			flow_controller.bsr(int8_t(src.b) + 2);
+			flow_controller.bsr(uint32_t(int8_t(src.b)));
 		break;
 		case Operation::BSRw:
-			flow_controller.bsr(int16_t(src.w) + 2);
+			flow_controller.bsr(uint32_t(int16_t(src.w)));
 		break;
 		case Operation::BSRl:
-			flow_controller.bsr(src.l + 2);
+			flow_controller.bsr(src.l);
 		break;
 
 		case Operation::DBcc: {
@@ -294,9 +294,11 @@ template <
 				int16_t(dest.w));
 		} break;
 
-		case Operation::Scc:
-			src.b = status.evaluate_condition(instruction.condition()) ? 0xff : 0x00;
-		break;
+		case Operation::Scc: {
+			const bool condition = status.evaluate_condition(instruction.condition());
+			src.b = condition ? 0xff : 0x00;
+			flow_controller.did_scc(condition);
+		} break;
 
 		/*
 			CLRs: store 0 to the destination, set the zero flag, and clear
@@ -520,17 +522,18 @@ template <
 #define DIV(Type16, Type32, flow_function) {								\
 	status.carry_flag = 0;													\
 																			\
-	if(!src.w) {															\
+	const auto dividend = Type32(dest.l);									\
+	const auto divisor = Type32(Type16(src.w));								\
+																			\
+	if(!divisor) {															\
 		status.negative_flag = status.overflow_flag = 0;					\
 		status.zero_result = 1;												\
 		flow_controller.raise_exception(Exception::IntegerDivideByZero);	\
+		flow_controller.template flow_function<false>(dividend, divisor);	\
 		return;																\
 	}																		\
 																			\
-	const auto dividend = Type32(dest.l);									\
-	const auto divisor = Type32(Type16(src.w));								\
-	const auto quotient = dividend / divisor;								\
-																			\
+	const auto quotient = int64_t(dividend) / int64_t(divisor);				\
 	if(quotient != Type32(Type16(quotient))) {								\
 		status.overflow_flag = 1;											\
 		flow_controller.template flow_function<true>(dividend, divisor);	\
@@ -553,7 +556,7 @@ template <
 
 		// TRAP, which is a nicer form of ILLEGAL.
 		case Operation::TRAP:
-			flow_controller.template raise_exception<false>(src.l + Exception::TrapBase);
+			flow_controller.template raise_exception<false>(int(src.l + Exception::TrapBase));
 		break;
 
 		case Operation::TRAPV: {
@@ -678,7 +681,7 @@ template <
 		*/
 
 		case Operation::LINKw:
-			flow_controller.link(instruction, int16_t(dest.w));
+			flow_controller.link(instruction, uint32_t(int16_t(dest.w)));
 		break;
 
 		case Operation::UNLINK:
@@ -825,14 +828,14 @@ template <
 	set_neg_zero(v, m);												\
 	status.overflow_flag = (Status::FlagT(value) ^ status.zero_result) & Status::FlagT(m);
 
-#define decode_shift_count()	\
+#define decode_shift_count(type)	\
 	int shift_count = src.l & 63;	\
-	flow_controller.did_shift(shift_count);
+	flow_controller.template did_shift<type>(shift_count);
 
 #define set_flags_w(t) set_flags(src.w, 0x8000, t)
 
 #define asl(destination, size)	{\
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination)); \
 	const auto value = destination;	\
 	\
 	if(!shift_count) {	\
@@ -862,7 +865,7 @@ template <
 		case Operation::ASLl: asl(dest.l, 32); 	break;
 
 #define asr(destination, size)	{\
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination));	\
 	const auto value = destination;	\
 	\
 	if(!shift_count) {	\
@@ -906,7 +909,7 @@ template <
 	status.carry_flag = value & (t);
 
 #define lsl(destination, size)	{\
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination));	\
 	const auto value = destination;	\
 	\
 	if(!shift_count) {	\
@@ -930,7 +933,7 @@ template <
 		case Operation::LSLl: lsl(dest.l, 32); 	break;
 
 #define lsr(destination, size)	{\
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination));	\
 	const auto value = destination;	\
 	\
 	if(!shift_count) {	\
@@ -954,7 +957,7 @@ template <
 		case Operation::LSRl: lsr(dest.l, 32); 	break;
 
 #define rol(destination, size)	{ \
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination));	\
 	const auto value = destination;	\
 	\
 	if(!shift_count) {	\
@@ -982,7 +985,7 @@ template <
 		case Operation::ROLl: rol(dest.l, 32); 	break;
 
 #define ror(destination, size)	{ \
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination));	\
 	const auto value = destination;	\
 	\
 	if(!shift_count) {	\
@@ -1010,7 +1013,7 @@ template <
 		case Operation::RORl: ror(dest.l, 32); 	break;
 
 #define roxl(destination, size)	{ \
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination));	\
 	\
 	shift_count %= (size + 1);	\
 	uint64_t compound = uint64_t(destination) | (status.extend_flag ? (1ull << size) : 0);	\
@@ -1034,7 +1037,7 @@ template <
 		case Operation::ROXLl: roxl(dest.l, 32); 	break;
 
 #define roxr(destination, size)	{ \
-	decode_shift_count();	\
+	decode_shift_count(decltype(destination));	\
 	\
 	shift_count %= (size + 1);	\
 	uint64_t compound = uint64_t(destination) | (status.extend_flag ? (1ull << size) : 0);	\
diff --git a/InstructionSets/M68k/Instruction.cpp b/InstructionSets/M68k/Instruction.cpp
index b4184c868..c52ebe0ee 100644
--- a/InstructionSets/M68k/Instruction.cpp
+++ b/InstructionSets/M68k/Instruction.cpp
@@ -61,7 +61,7 @@ std::string Preinstruction::to_string(int opcode) const {
 	const char *instruction;
 
 	switch(operation) {
-		case Operation::Undefined:	instruction = "None";		break;
+		case Operation::Undefined:	return "None";
 		case Operation::NOP:		instruction = "NOP";		break;
 		case Operation::ABCD:		instruction = "ABCD";		break;
 		case Operation::SBCD:		instruction = "SBCD";		break;
diff --git a/InstructionSets/M68k/Instruction.hpp b/InstructionSets/M68k/Instruction.hpp
index a016fac9c..314729f8d 100644
--- a/InstructionSets/M68k/Instruction.hpp
+++ b/InstructionSets/M68k/Instruction.hpp
@@ -135,7 +135,8 @@ enum class DataSize {
 /// For any operations that don't fit the neat model of reading one or two operands,
 /// then writing zero or one, the size determines the data size of the operands only,
 /// not any other accesses.
-constexpr DataSize operand_size(Operation operation);
+template <Operation t_operation = Operation::Undefined>
+constexpr DataSize operand_size(Operation operation = Operation::Undefined);
 
 template <Operation t_op = Operation::Undefined>
 constexpr uint32_t quick(uint16_t instruction, Operation r_op = Operation::Undefined) {
@@ -165,7 +166,7 @@ static constexpr uint8_t StoreOp2	= (1 << 3);
 	Unusual bus sequences, such as TAS or MOVEM, are not described here.
 */
 template <Model model, Operation t_operation = Operation::Undefined>
-uint8_t operand_flags(Operation r_operation = Operation::Undefined);
+constexpr uint8_t operand_flags(Operation r_operation = Operation::Undefined);
 
 /// Lists the various condition codes used by the 680x0.
 enum class Condition {
diff --git a/InstructionSets/M68k/Perform.hpp b/InstructionSets/M68k/Perform.hpp
index 6351b1448..300706b00 100644
--- a/InstructionSets/M68k/Perform.hpp
+++ b/InstructionSets/M68k/Perform.hpp
@@ -32,8 +32,11 @@ struct NullFlowController {
 	/// Indicates that a @c CHK was performed, along with whether the result @c was_under zero or @c was_over the source operand.
 	void did_chk([[maybe_unused]] bool was_under, [[maybe_unused]] bool was_over) {}
 
-	/// Indicates an in-register shift or roll occurred, providing the number of bits shifted by.
-	void did_shift([[maybe_unused]] int bit_count) {}
+	/// Indicates an in-register shift or roll occurred, providing the number of bits shifted by
+	/// and the type shifted.
+	///
+	/// @c IntT may be uint8_t, uint16_t or uint32_t.
+	template <typename IntT> void did_shift([[maybe_unused]] int bit_count) {}
 
 	/// Indicates that a @c DIVU was performed, providing the @c dividend and @c divisor.
 	/// If @c did_overflow is @c true then the divide ended in overflow.
@@ -46,6 +49,10 @@ struct NullFlowController {
 	/// Indicates that a bit-manipulation operation (i.e. BTST, BCHG or BSET) was performed, affecting the bit at posiition @c bit_position.
 	void did_bit_op([[maybe_unused]] int bit_position) {}
 
+	/// Indicates that an @c Scc was performed; if @c did_set_ff is true then the condition was true and FF
+	/// written to the operand; otherwise 00 was written.
+	void did_scc([[maybe_unused]] bool did_set_ff) {}
+
 	/// Provides a notification that the upper byte of the status register has been affected by the current instruction;
 	/// this gives an opportunity to track the supervisor flag.
 	void did_update_status() {}
diff --git a/InstructionSets/M68k/RegisterSet.hpp b/InstructionSets/M68k/RegisterSet.hpp
new file mode 100644
index 000000000..87e98f70b
--- /dev/null
+++ b/InstructionSets/M68k/RegisterSet.hpp
@@ -0,0 +1,31 @@
+//
+//  RegisterSet.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 16/05/2022.
+//  Copyright © 2022 Thomas Harte. All rights reserved.
+//
+
+#ifndef InstructionSets_M68k_RegisterSet_h
+#define InstructionSets_M68k_RegisterSet_h
+
+namespace InstructionSet {
+namespace M68k {
+
+struct RegisterSet {
+	uint32_t data[8], address[7];
+	uint32_t user_stack_pointer;
+	uint32_t supervisor_stack_pointer;
+	uint16_t status;
+	uint32_t program_counter;
+
+	/// @returns The active stack pointer, whichever it may be.
+	uint32_t stack_pointer() const {
+		return (status & 0x2000) ? supervisor_stack_pointer : user_stack_pointer;
+	}
+};
+
+}
+}
+
+#endif /* InstructionSets_M68k_RegisterSet_h */
diff --git a/InstructionSets/M68k/Status.hpp b/InstructionSets/M68k/Status.hpp
index c0af4d9f8..583d4fe3b 100644
--- a/InstructionSets/M68k/Status.hpp
+++ b/InstructionSets/M68k/Status.hpp
@@ -22,6 +22,8 @@ static constexpr uint16_t Zero			= 1 << 2;
 static constexpr uint16_t Negative		= 1 << 3;
 static constexpr uint16_t Extend		= 1 << 4;
 
+static constexpr uint16_t AllConditions	= Carry | Overflow | Zero | Negative | Extend;
+
 static constexpr uint16_t Supervisor	= 1 << 13;
 static constexpr uint16_t Trace			= 1 << 15;
 
@@ -93,8 +95,25 @@ struct Status {
 		return is_supervisor;
 	}
 
+	/// Adjusts the status for exception processing — sets supervisor mode, disables trace,
+	/// and if @c new_interrupt_level is greater than or equal to 0 sets that as the new
+	/// interrupt level.
+	///
+	/// @returns The status prior to those changes.
+	uint16_t begin_exception(int new_interrupt_level = -1) {
+		const uint16_t initial_status = status();
+
+		if(new_interrupt_level >= 0) {
+			interrupt_level = new_interrupt_level;
+		}
+		is_supervisor = true;
+		trace_flag = 0;
+
+		return initial_status;
+	}
+
 	/// Evaluates @c condition.
-	bool evaluate_condition(Condition condition) {
+	constexpr bool evaluate_condition(Condition condition) const {
 		switch(condition) {
 			default:
 			case Condition::True:			return true;
@@ -119,6 +138,13 @@ struct Status {
 				return !zero_result || (negative_flag && !overflow_flag) || (!negative_flag && overflow_flag);
 		}
 	}
+
+	/// @returns @c true if an interrupt at level @c level should be accepted; @c false otherwise.
+	constexpr bool would_accept_interrupt(int level) const {
+		// TODO: is level seven really non-maskable? If so then what mechanism prevents
+		// rapid stack overflow upon a level-seven interrupt?
+		return level > interrupt_level;
+	}
 };
 
 }
diff --git a/Machines/Apple/Macintosh/Macintosh.cpp b/Machines/Apple/Macintosh/Macintosh.cpp
index bf9f06e9d..0b6ab4374 100644
--- a/Machines/Apple/Macintosh/Macintosh.cpp
+++ b/Machines/Apple/Macintosh/Macintosh.cpp
@@ -36,6 +36,8 @@
 #include "../../../Components/DiskII/MacintoshDoubleDensityDrive.hpp"
 #include "../../../Processors/68000/68000.hpp"
 
+#include "../../../Processors/68000Mk2/68000Mk2.hpp"
+
 #include "../../../Storage/MassStorage/SCSI/SCSI.hpp"
 #include "../../../Storage/MassStorage/SCSI/DirectAccessDevice.hpp"
 #include "../../../Storage/MassStorage/Encodings/MacintoshVolume.hpp"
diff --git a/Numeric/RegisterSizes.hpp b/Numeric/RegisterSizes.hpp
index 39321ffc0..2c0363595 100644
--- a/Numeric/RegisterSizes.hpp
+++ b/Numeric/RegisterSizes.hpp
@@ -72,6 +72,14 @@ template <> union SlicedInt<uint32_t> {
 #endif
 		uint8_t b;
 	};
+
+	struct {
+#if TARGET_RT_BIG_ENDIAN
+		SlicedInt<uint16_t> high, low;
+#else
+		SlicedInt<uint16_t> low, high;
+#endif
+	};
 };
 
 using SlicedInt16 = SlicedInt<uint16_t>;
diff --git a/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj b/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj
index 053a482eb..47c6a8f14 100644
--- a/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj	
+++ b/OSBindings/Mac/Clock Signal.xcodeproj/project.pbxproj	
@@ -1680,6 +1680,7 @@
 		4BA0F68C1EEA0E8400E9489E /* ZX8081.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = ZX8081.cpp; sourceTree = "<group>"; };
 		4BA0F68D1EEA0E8400E9489E /* ZX8081.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = ZX8081.hpp; sourceTree = "<group>"; };
 		4BA141C12073100800A31EC9 /* Target.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = Target.hpp; sourceTree = "<group>"; };
+		4BA3AE44283317CB00328FED /* RegisterSet.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = RegisterSet.hpp; sourceTree = "<group>"; };
 		4BA61EAE1D91515900B3C876 /* NSData+StdVector.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; path = "NSData+StdVector.h"; sourceTree = "<group>"; };
 		4BA61EAF1D91515900B3C876 /* NSData+StdVector.mm */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.objcpp; path = "NSData+StdVector.mm"; sourceTree = "<group>"; };
 		4BA91E1C216D85BA00F79557 /* MasterSystemVDPTests.mm */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.objcpp; path = MasterSystemVDPTests.mm; sourceTree = "<group>"; };
@@ -2065,6 +2066,9 @@
 		4BC9DF4D1D04691600F44158 /* 6560.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = 6560.cpp; sourceTree = "<group>"; };
 		4BC9DF4E1D04691600F44158 /* 6560.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 6560.hpp; sourceTree = "<group>"; };
 		4BC9E1ED1D23449A003FCEE4 /* 6502InterruptTests.swift */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.swift; path = 6502InterruptTests.swift; sourceTree = "<group>"; };
+		4BCA2F562832A643006C632A /* 68000Mk2.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 68000Mk2.hpp; sourceTree = "<group>"; };
+		4BCA2F592832A807006C632A /* 68000Mk2Storage.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 68000Mk2Storage.hpp; sourceTree = "<group>"; };
+		4BCA2F5A2832A81C006C632A /* 68000Mk2Implementation.hpp */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.cpp.h; path = 68000Mk2Implementation.hpp; sourceTree = "<group>"; };
 		4BCA6CC61D9DD9F000C2D7B2 /* CommodoreROM.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = CommodoreROM.cpp; path = Encodings/CommodoreROM.cpp; sourceTree = "<group>"; };
 		4BCA6CC71D9DD9F000C2D7B2 /* CommodoreROM.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; name = CommodoreROM.hpp; path = Encodings/CommodoreROM.hpp; sourceTree = "<group>"; };
 		4BCA98C21D065CA20062F44C /* 6522.hpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.h; path = 6522.hpp; sourceTree = "<group>"; };
@@ -3218,6 +3222,7 @@
 				4B79629C2819681F008130F9 /* Instruction.hpp */,
 				4B79629D2819681F008130F9 /* Model.hpp */,
 				4BB5B996281B1E3F00522DA9 /* Perform.hpp */,
+				4BA3AE44283317CB00328FED /* RegisterSet.hpp */,
 				4BB5B997281B1F7B00522DA9 /* Status.hpp */,
 				4BB5B999281B244400522DA9 /* Implementation */,
 			);
@@ -4334,6 +4339,7 @@
 				4B4DEC15252BFA9C004583AC /* 6502Esque */,
 				4BF8D4CC251C0C9C00BBE21B /* 65816 */,
 				4BFF1D332233778C00838EA1 /* 68000 */,
+				4BCA2F552832A643006C632A /* 68000Mk2 */,
 				4B77069E1EC9045B0053B588 /* Z80 */,
 			);
 			name = Processors;
@@ -4561,6 +4567,24 @@
 			path = 6560;
 			sourceTree = "<group>";
 		};
+		4BCA2F552832A643006C632A /* 68000Mk2 */ = {
+			isa = PBXGroup;
+			children = (
+				4BCA2F562832A643006C632A /* 68000Mk2.hpp */,
+				4BCA2F582832A807006C632A /* Implementation */,
+			);
+			path = 68000Mk2;
+			sourceTree = "<group>";
+		};
+		4BCA2F582832A807006C632A /* Implementation */ = {
+			isa = PBXGroup;
+			children = (
+				4BCA2F592832A807006C632A /* 68000Mk2Storage.hpp */,
+				4BCA2F5A2832A81C006C632A /* 68000Mk2Implementation.hpp */,
+			);
+			path = Implementation;
+			sourceTree = "<group>";
+		};
 		4BCA6CC91D9DD9F500C2D7B2 /* Encodings */ = {
 			isa = PBXGroup;
 			children = (
diff --git a/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm b/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm
index f0fb7aa49..7aabcd052 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ArithmeticTests.mm	
@@ -42,14 +42,14 @@
 	self.machine->set_program({
 		0x0602, 0xff		// ADD.B #$ff, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x9ae;
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0x9ae;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Extend);
-	XCTAssertEqual(state.data[2], 0x9ad);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x9ad);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -57,14 +57,14 @@
 	self.machine->set_program({
 		0xd43c, 0x82		// ADD.B #$82, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x82;
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0x82;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Carry | Flag::Extend);
-	XCTAssertEqual(state.data[2], 0x04);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x04);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -72,15 +72,15 @@
 	self.machine->set_program({
 		0xd538, 0x3000		// ADD.B D2, ($3000).W
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x82;
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0x82;
+	});
 	*self.machine->ram_at(0x3000) = 0x8200;
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Carry | Flag::Extend);
-	XCTAssertEqual(state.data[2], 0x82);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x82);
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x0400);
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 }
@@ -89,13 +89,13 @@
 	self.machine->set_program({
 		0xd442		// ADD.W D2, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x3e8;
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0x3e8;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x7D0);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[2], 0x7D0);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -103,20 +103,19 @@
 	self.machine->set_program({
 		0xd59a		// ADD.L D2, (A2)+
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0xb2d05e00;
-	state.address[2] = 0x2000;
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0xb2d05e00;
+		registers.address[2] = 0x2000;
+	});
 	*self.machine->ram_at(0x2000) = 0x7735;
 	*self.machine->ram_at(0x2002) = 0x9400;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xb2d05e00);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[2], 0xb2d05e00);
 	XCTAssertEqual(*self.machine->ram_at(0x2000), 0x2a05);
 	XCTAssertEqual(*self.machine->ram_at(0x2002), 0xf200);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -124,19 +123,18 @@
 	self.machine->set_program({
 		0xd462		// ADD.W -(A2), D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0xFFFF0000;
-	state.address[2] = 0x2002;
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0xFFFF0000;
+		registers.address[2] = 0x2002;
+	});
 	*self.machine->ram_at(0x2000) = 0;
 	*self.machine->ram_at(0x2002) = 0xffff;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xFFFF0000);
-	XCTAssertEqual(state.address[2], 0x2000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[2], 0xFFFF0000);
+	XCTAssertEqual(state.registers.address[2], 0x2000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(10, self.machine->get_cycle_count());
 }
 
@@ -149,17 +147,16 @@
 	self.machine->set_program({
 		0xd481		// ADD.l D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xfe35aab0;
-	state.data[2] = 0x012557ac;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xfe35aab0;
+		registers.data[2] = 0x012557ac;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xfe35aab0);
-	XCTAssertEqual(state.data[2], 0xff5b025c);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xfe35aab0);
+	XCTAssertEqual(state.registers.data[2], 0xff5b025c);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -175,83 +172,79 @@
 	self.machine->set_program({
 		0xd5fc, 0x1234, 0x5678		// ADDA.L #$12345678, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status = Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xae43ab1d;
+		registers.status = ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xc0780195);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0xc0780195);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDAWPositive {
 	self.machine->set_program({
 		0xd4fc, 0x5678		// ADDA.W #$5678, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status = Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xae43ab1d;
+		registers.status = ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xae440195);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0xae440195);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDAWNegative {
 	self.machine->set_program({
 		0xd4fc, 0xf678		// ADDA.W #$f678, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status = Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xae43ab1d;
+		registers.status = ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xae43a195);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0xae43a195);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDAWNegative_2 {
 	self.machine->set_program({
 		0xd4fc, 0xf000		// ADDA.W #$f000, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.status = Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.status = ConditionCode::AllConditions;
+		registers.address[2] = 0;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xfffff000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0xfffff000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testADDALPreDec {
 	self.machine->set_program({
 		0xd5e2				// ADDA.L -(A2), A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.status = Flag::ConditionCodes;
-	state.address[2] = 0x2004;
+	self.machine->set_registers([=](auto &registers) {
+		registers.status = ConditionCode::AllConditions;
+		registers.address[2] = 0x2004;
+	});
 	*self.machine->ram_at(0x2000) = 0x7002;
 	*self.machine->ram_at(0x2002) = 0;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x70022000);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0x70022000);
 	XCTAssertEqual(*self.machine->ram_at(0x2000), 0x7002);
 	XCTAssertEqual(*self.machine->ram_at(0x2002), 0x0000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 @end
@@ -266,18 +259,17 @@
 	self.machine->set_program({
 		0xd581		// ADDX.l D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x12345678;
-	state.data[2] = 0x12345678;
-	state.status |= Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x12345678;
+		registers.data[2] = 0x12345678;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0x2468acf1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0x2468acf1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -285,17 +277,16 @@
 	self.machine->set_program({
 		0xd501		// ADDX.b D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x80;
-	state.data[2] = 0x8080;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x80;
+		registers.data[2] = 0x8080;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x80);
-	XCTAssertEqual(state.data[2], 0x8000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Overflow | Flag::Extend);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x80);
+	XCTAssertEqual(state.registers.data[2], 0x8000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Extend);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -303,18 +294,17 @@
 	self.machine->set_program({
 		0xd541		// ADDX.w D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x1ffff;
-	state.data[2] = 0x18080;
-	state.status |= Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x1ffff;
+		registers.data[2] = 0x18080;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1ffff);
-	XCTAssertEqual(state.data[2], 0x18080);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Extend);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x1ffff);
+	XCTAssertEqual(state.registers.data[2], 0x18080);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Extend);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -322,20 +312,19 @@
 	self.machine->set_program({
 		0xd389		// ADDX.l -(A1), -(A1)
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.status |= Flag::ConditionCodes;
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	*self.machine->ram_at(0x2ff8) = 0x1000;
 	*self.machine->ram_at(0x2ffa) = 0x0000;
 	*self.machine->ram_at(0x2ffc) = 0x7000;
 	*self.machine->ram_at(0x2ffe) = 0x1ff1;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2ff8);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x2ff8);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(*self.machine->ram_at(0x2ff8), 0x8000);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffa), 0x1ff2);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffc), 0x7000);
@@ -355,15 +344,14 @@
 	self.machine->set_program({
 		0x0681, 0x1111, 0x1111		// ADDI.l #$11111111, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x300021b3;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x300021b3;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x411132C4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x411132C4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 }
 
@@ -377,7 +365,7 @@
 
 	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x2554);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -393,15 +381,14 @@
 	self.machine->set_program({
 		0x5e81		// ADDQ.l #$7, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xffffffff;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xffffffff;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x6);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x6);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -409,15 +396,14 @@
 	self.machine->set_program({
 		0x5641		// ADDQ.W #$3, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xfffffffe;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xfffffffe;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffff0001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xffff0001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
@@ -425,15 +411,14 @@
 	self.machine->set_program({
 		0x5649		// ADDQ.W #$3, A1
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[1] = 0xfffffffe;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0xfffffffe;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -447,7 +432,7 @@
 
 	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x8005);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow);
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 }
 
@@ -463,69 +448,66 @@
 	self.machine->set_program({
 		opcode
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x1234567f;
-	state.data[2] = 0x12345680;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x1234567f;
+		registers.data[2] = 0x12345680;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234567f);
-	XCTAssertEqual(state.data[2], 0x12345680);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, flags);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x1234567f);
+	XCTAssertEqual(state.registers.data[2], 0x12345680);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, flags);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
 - (void)testCMPb_D1D2 {
-	[self performCMPb:0xb401 expectedFlags:Flag::Overflow];	// CMP.b D1, D2
+	[self performCMPb:0xb401 expectedFlags:ConditionCode::Overflow];	// CMP.b D1, D2
 }
 
 - (void)testCMPb_D2D1 {
-	[self performCMPb:0xb202 expectedFlags:Flag::Overflow | Flag::Negative | Flag::Carry];	// CMP.b D2, D1
+	[self performCMPb:0xb202 expectedFlags:ConditionCode::Overflow | ConditionCode::Negative | ConditionCode::Carry];	// CMP.b D2, D1
 }
 
 - (void)performCMPwd1:(uint32_t)d1 d2:(uint32_t)d2 expectedFlags:(uint16_t)flags {
 	self.machine->set_program({
 		0xb242		// CMP.W D2, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.data[2] = d2;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.data[2], d2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, flags);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.data[2], d2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, flags);
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 }
 
 - (void)testCMPw_8004v7002 {
-	[self performCMPwd1:0x12347002 d2:0x12348004 expectedFlags:Flag::Overflow | Flag::Negative | Flag::Carry];
+	[self performCMPwd1:0x12347002 d2:0x12348004 expectedFlags:ConditionCode::Overflow | ConditionCode::Negative | ConditionCode::Carry];
 }
 
 - (void)testCMPw_6666v5555 {
-	[self performCMPwd1:0x55555555 d2:0x66666666 expectedFlags:Flag::Negative | Flag::Carry];
+	[self performCMPwd1:0x55555555 d2:0x66666666 expectedFlags:ConditionCode::Negative | ConditionCode::Carry];
 }
 
 - (void)testCMPl {
 	self.machine->set_program({
 		0xb282		// CMP.l D2, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x12347002;
-	state.data[2] = 0x12348004;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x12347002;
+		registers.data[2] = 0x12348004;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12347002);
-	XCTAssertEqual(state.data[2], 0x12348004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x12347002);
+	XCTAssertEqual(state.registers.data[2], 0x12348004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(6, self.machine->get_cycle_count());
 }
 
@@ -541,16 +523,15 @@
 	self.machine->set_program({
 		0xb5c1		// CMPA.l D1, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.address[2] = a2;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.address[2] = a2;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[2], a2);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[2], a2);
 	XCTAssertEqual(6, self.machine->get_cycle_count());
 }
 
@@ -558,37 +539,36 @@
 	[self performCMPAld1:0x1234567f a2:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testCMPAl_carry {
 	[self performCMPAld1:0xfd234577 a2:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry);
 }
 
 - (void)testCMPAl_carryOverflowNegative {
 	[self performCMPAld1:0x85678943 a2:0x22563245];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Overflow | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Negative);
 }
 
 - (void)performCMPAwd1:(uint32_t)d1 a2:(uint32_t)a2 {
 	self.machine->set_program({
 		0xb4c1		// CMPA.w D1, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.address[2] = a2;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.address[2] = a2;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[2], a2);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[2], a2);
 	XCTAssertEqual(6, self.machine->get_cycle_count());
 }
 
@@ -596,14 +576,14 @@
 	[self performCMPAwd1:0x85678943 a2:0x22563245];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry);
 }
 
 - (void)testCMPAw_zero {
 	[self performCMPAwd1:0x0000ffff a2:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 @end
@@ -618,15 +598,14 @@
 	self.machine->set_program({
 		0x0c41, 0xffff		// CMPI.W #$ffff, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xfff2ffff;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xfff2ffff;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xfff2ffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xfff2ffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -634,15 +613,14 @@
 	self.machine->set_program({
 		0x0c81, 0x8000, 0x0000		// CMPI.L #$80000000, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x7fffffff;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x7fffffff;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x7fffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow | Flag::Carry);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x7fffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry);
 	XCTAssertEqual(14, self.machine->get_cycle_count());
 }
 
@@ -650,15 +628,14 @@
 	self.machine->set_program({
 		0x0c01, 0x0090		// CMPI.B #$90, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x8f;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x8f;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x8f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x8f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(8, self.machine->get_cycle_count());
 }
 
@@ -674,20 +651,19 @@
 	self.machine->set_program({
 		0xb389		// CMPM.L (A1)+, (A1)+
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.status |= Flag::ConditionCodes;
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	*self.machine->ram_at(0x3000) = 0x7000;
 	*self.machine->ram_at(0x3002) = 0x1ff1;
 	*self.machine->ram_at(0x3004) = 0x1000;
 	*self.machine->ram_at(0x3006) = 0x0000;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3008);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x3008);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -695,20 +671,19 @@
 	self.machine->set_program({
 		0xb549		// CMPM.w (A1)+, (A2)+
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.address[2] = 0x3002;
-	state.status |= Flag::ConditionCodes;
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+		registers.address[2] = 0x3002;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	*self.machine->ram_at(0x3000) = 0;
 	*self.machine->ram_at(0x3002) = 0;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3002);
-	XCTAssertEqual(state.address[2], 0x3004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero | Flag::Extend);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x3002);
+	XCTAssertEqual(state.registers.address[2], 0x3004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero | ConditionCode::Extend);
 	XCTAssertEqual(12, self.machine->get_cycle_count());
 }
 
@@ -716,19 +691,18 @@
 	self.machine->set_program({
 		0xb509		// CMPM.b (A1)+, (A2)+
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.address[2] = 0x3001;
-	state.status |= Flag::ConditionCodes;
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+		registers.address[2] = 0x3001;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	*self.machine->ram_at(0x3000) = 0x807f;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3001);
-	XCTAssertEqual(state.address[2], 0x3002);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry | Flag::Overflow);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x3001);
+	XCTAssertEqual(state.registers.address[2], 0x3002);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 	XCTAssertEqual(12, self.machine->get_cycle_count());
 }
 
@@ -740,24 +714,32 @@
 @end
 @implementation M68000DIVSTests
 
-- (void)performDIVS:(uint16_t)divisor d1:(uint32_t)d1 {
+- (void)performDIVS:(uint16_t)divisor d1:(uint32_t)d1 sp:(uint32_t)sp {
 	self.machine->set_program({
 		0x83fc, divisor		// DIVS #divisor, D1
+	}, sp);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.status |= ConditionCode::AllConditions;
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.status |= Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 }
 
+- (void)performDIVS:(uint16_t)divisor d1:(uint32_t)d1 {
+	[self performDIVS:divisor d1:d1 sp:0];
+}
+
 - (void)performDIVSOverflowTestDivisor:(uint16_t)divisor {
 	[self performDIVS:divisor d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x4768f231);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x4768f231);
+
+	// N and Z are officially undefined upon DIVS overflow, and I've found no
+	// other relevant information.
+	XCTAssertEqual(
+		state.registers.status & (ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry),
+		ConditionCode::Extend | ConditionCode::Overflow);
 	XCTAssertEqual(20, self.machine->get_cycle_count());
 }
 
@@ -777,8 +759,8 @@
 	[self performDIVS:0xeef0 d1:0x0768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x026190D3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x026190D3);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(138, self.machine->get_cycle_count());
 }
 
@@ -786,8 +768,8 @@
 	[self performDIVS:0xffff d1:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -795,8 +777,8 @@
 	[self performDIVS:0x3333 d1:0xffff0000];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xfffffffb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xfffffffb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -804,8 +786,8 @@
 	[self performDIVS:0x23 d1:0x8765];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xb03de);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0xb03de);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(138, self.machine->get_cycle_count());
 }
 
@@ -813,8 +795,8 @@
 	[self performDIVS:0x8765 d1:0x65];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x650000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x650000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(156, self.machine->get_cycle_count());
 }
 
@@ -823,8 +805,10 @@
 	[self performDIVS:0xffff d1:0x80000000];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x80000000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x80000000);
+	XCTAssertEqual(
+		state.registers.status & (ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry),
+		ConditionCode::Extend | ConditionCode::Overflow);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -833,8 +817,8 @@
 	[self performDIVS:0xfffd d1:0xfffffffd];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(158, self.machine->get_cycle_count());
 }
 
@@ -843,8 +827,8 @@
 	[self performDIVS:0x7aee d1:0xdaaa00fe];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xc97eb240);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xc97eb240);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(148, self.machine->get_cycle_count());
 }
 
@@ -853,8 +837,8 @@
 	[self performDIVS:0x7fff d1:0x82f9fff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x305e105f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x305e105f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(142, self.machine->get_cycle_count());
 }
 
@@ -863,32 +847,40 @@
 	[self performDIVS:0xf32 d1:0x00e1d44];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x0bfa00ed);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x0bfa00ed);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(144, self.machine->get_cycle_count());
 }
 
 - (void)testDIVS_12 {
 	// DIVS.W #$af32, D1
-	[self performDIVS:0xaf32 d1:0xe1d44];
+	[self performDIVS:0xaf32 d1:0xe1d44 sp:0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x39dcffd4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x39dcffd4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(150, self.machine->get_cycle_count());
 }
 
 - (void)testDIVSException {
 	// DIVS.W #0, D1
 	const uint32_t initial_sp = 0x5000;
-	self.machine->set_initial_stack_pointer(initial_sp);
-	[self performDIVS:0x0 d1:0x1fffffff];
+	[self performDIVS:0x0 d1:0x1fffffff sp:initial_sp];
 
-	// Check register state.
+	// Check register state.registers.
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1fffffff);
-	XCTAssertEqual(state.supervisor_stack_pointer, initial_sp - 6);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x1fffffff);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, initial_sp - 6);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
+
+	// Total expected bus pattern:
+	//
+	// np | nn nn | nw nw nw np np np n np = 42 cycles
+	//
+	// Noted: Yacht shows a total of three nps for a DIVS #;
+	// I believe this is incorrect as it includes two in the
+	// '1st op (ea)' stage, but an immediate word causes
+	// only one elsewhere.
 	XCTAssertEqual(42, self.machine->get_cycle_count());
 
 	// Check stack contents; should be PC.l, PC.h and status register.
@@ -915,11 +907,10 @@
 	self.machine->set_program({
 		0x82fc, divisor		// DIVU #$eef0, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.status |= Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 }
 
@@ -927,8 +918,12 @@
 	[self performDIVU:1 d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x4768f231);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x4768f231);
+
+	// This test should produce overflow; so don't test N or Z flags.
+	XCTAssertEqual(
+		state.registers.status & (ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Extend),
+		ConditionCode::Extend | ConditionCode::Overflow);
 	XCTAssertEqual(14, self.machine->get_cycle_count());
 }
 
@@ -936,8 +931,11 @@
 	[self performDIVU:0x1234 d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x4768f231);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x4768f231);
+	// This test should also produce overflow; so don't test N or Z flags.
+	XCTAssertEqual(
+		state.registers.status & (ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Extend),
+		ConditionCode::Extend | ConditionCode::Overflow);
 	XCTAssertEqual(14, self.machine->get_cycle_count());
 }
 
@@ -945,8 +943,8 @@
 	[self performDIVU:0xeeff d1:0x4768f231];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x8bae4c7d);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x8bae4c7d);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(108, self.machine->get_cycle_count());
 }
 
@@ -954,8 +952,8 @@
 	[self performDIVU:0x3333 d1:0x1fffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1fffa000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x1fffa000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(136, self.machine->get_cycle_count());
 }
 
@@ -974,11 +972,10 @@
 		0x4883		// EXT.W D3
 	});
 
-	auto state = self.machine->get_processor_state();
-	state.data[3] = d3;
-	state.status = 0x13;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[3] = d3;
+		registers.status = 0x13;
+	});
 	self.machine->run_for_instructions(1);
 
 	XCTAssertEqual(4, self.machine->get_cycle_count());
@@ -988,24 +985,24 @@
 	[self performEXTwd3:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x12340078);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[3], 0x12340078);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testEXTw_00 {
 	[self performEXTwd3:0x12345600];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x12340000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[3], 0x12340000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 }
 
 - (void)testEXTw_f0 {
 	[self performEXTwd3:0x123456f0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x1234fff0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[3], 0x1234fff0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testEXTl {
@@ -1013,18 +1010,17 @@
 		0x48c3		// EXT.L D3
 	});
 
-	auto state = self.machine->get_processor_state();
-	state.data[3] = 0x1234f6f0;
-	state.status = 0x13;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[3] = 0x1234f6f0;
+		registers.status = 0x13;
+	});
 	self.machine->run_for_instructions(1);
 
 	XCTAssertEqual(4, self.machine->get_cycle_count());
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0xfffff6f0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0xfffff6f0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 }
 
 @end
@@ -1039,12 +1035,11 @@
 	self.machine->set_program({
 		0xc5c1		// MULS D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
-	state.status = ccr;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.data[2] = d2;
+		registers.status = ccr;
+	});
 	self.machine->run_for_instructions(1);
 }
 
@@ -1052,11 +1047,10 @@
 	self.machine->set_program({
 		0xc5fc, constant		// MULS #constant, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = d2;
-	state.status = Flag::Carry | Flag::Extend | Flag::Overflow;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = d2;
+		registers.status = ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Overflow;
+	});
 	self.machine->run_for_instructions(1);
 }
 
@@ -1064,9 +1058,9 @@
 	[self performMULSd1:0x12345678 d2:0x12345678 ccr:0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0x1d34d840);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0x1d34d840);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(54, self.machine->get_cycle_count());
 }
 
@@ -1074,19 +1068,19 @@
 	[self performMULSd1:0x82348678 d2:0x823486ff ccr:0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x82348678);
-	XCTAssertEqual(state.data[2], 0x3971c188);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x82348678);
+	XCTAssertEqual(state.registers.data[2], 0x3971c188);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(48, self.machine->get_cycle_count());
 }
 
 - (void)testMULSZero {
-	[self performMULSd1:1 d2:0 ccr:Flag::Carry | Flag::Overflow | Flag::Extend];
+	[self performMULSd1:1 d2:0 ccr:ConditionCode::Carry | ConditionCode::Overflow | ConditionCode::Extend];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 1);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 1);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(42, self.machine->get_cycle_count());
 }
 
@@ -1094,8 +1088,8 @@
 	[self performMULSConstant:0xffff d2:0xffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(44, self.machine->get_cycle_count());
 }
 
@@ -1103,8 +1097,8 @@
 	[self performMULSConstant:0x1fff d2:0x8fff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xf2005001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[2], 0xf2005001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(46, self.machine->get_cycle_count());
 }
 
@@ -1120,12 +1114,11 @@
 	self.machine->set_program({
 		0xc4c1		// MULU D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
-	state.status |= ccr;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.data[2] = d2;
+		registers.status |= ccr;
+	});
 	self.machine->run_for_instructions(1);
 }
 
@@ -1133,18 +1126,18 @@
 	[self performMULUd1:0x12345678 d2:0x12345678 ccr:0];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x1d34d840);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[2], 0x1d34d840);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(54, self.machine->get_cycle_count());
 }
 
 - (void)testMULU_Dn_Zero {
-	[self performMULUd1:1 d2:0 ccr:Flag::Extend | Flag::Overflow | Flag::Carry];
+	[self performMULUd1:1 d2:0 ccr:ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 1);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 1);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(40, self.machine->get_cycle_count());
 }
 
@@ -1152,16 +1145,15 @@
 	self.machine->set_program({
 		0xc4fc, 0xffff		// MULU.W	#$ffff, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0xffff;
-	state.status |= Flag::Extend | Flag::Overflow | Flag::Carry;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0xffff;
+		registers.status |= ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xfffe0001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	const auto state = self.machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[2], 0xfffe0001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(74, self.machine->get_cycle_count());
 }
 
@@ -1177,10 +1169,9 @@
 	self.machine->set_program({
 		0x4400		// NEG.b D0
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[0] = value;
+	});
 	self.machine->run_for_instructions(1);
 
 	XCTAssertEqual(4, self.machine->get_cycle_count());
@@ -1190,50 +1181,48 @@
 	[self performNEGb:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345688);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x12345688);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGb_00 {
 	[self performNEGb:0x12345600];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testNEGb_80 {
 	[self performNEGb:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345680);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x12345680);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)testNEGw {
 	self.machine->set_program({
 		0x4440		// NEG.w D0
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[0] = 0x12348000;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0x12348000;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(4, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0x12348000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Overflow | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x12348000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)performNEGl:(uint32_t)value {
 	self.machine->set_program({
 		0x4480		// NEG.l D0
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[0] = value;
+	});
 	self.machine->run_for_instructions(1);
 
 	XCTAssertEqual(6, self.machine->get_cycle_count());
@@ -1243,16 +1232,16 @@
 	[self performNEGl:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xedcba988);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xedcba988);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGl_small {
 	[self performNEGl:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testNEGl_XXXl {
@@ -1268,7 +1257,7 @@
 	XCTAssertEqual(28, self.machine->get_cycle_count());
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x0ffe);
 	XCTAssertEqual(*self.machine->ram_at(0x3002), 0xdcef);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 @end
@@ -1283,11 +1272,10 @@
 	self.machine->set_program({
 		0x4000		// NEGX.b D0
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
-	state.status |= Flag::Extend;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[0] = value;
+		registers.status |= ConditionCode::Extend;
+	});
 	self.machine->run_for_instructions(1);
 
 	XCTAssertEqual(4, self.machine->get_cycle_count());
@@ -1297,52 +1285,50 @@
 	[self performNEGXb:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345687);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x12345687);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGXb_00 {
 	[self performNEGXb:0x12345600];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x123456ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0x123456ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGXb_80 {
 	[self performNEGXb:0x12345680];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1234567f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x1234567f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)testNEGXw {
 	self.machine->set_program({
 		0x4040		// NEGX.w D0
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[0] = 0x12348000;
-	state.status |= Flag::Extend;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0x12348000;
+		registers.status |= ConditionCode::Extend;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(4, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0x12347fff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0x12347fff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 - (void)performNEGXl:(uint32_t)value {
 	self.machine->set_program({
 		0x4080		// NEGX.l D0
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[0] = value;
-	state.status |= Flag::Extend;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[0] = value;
+		registers.status |= ConditionCode::Extend;
+	});
 	self.machine->run_for_instructions(1);
 
 	XCTAssertEqual(6, self.machine->get_cycle_count());
@@ -1352,35 +1338,34 @@
 	[self performNEGXl:0x12345678];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xedcba987);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xedcba987);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 }
 
 - (void)testNEGXl_small {
 	[self performNEGXl:0xffffffff];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[0], 0x0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testNEGXl_XXXl {
 	self.machine->set_program({
 		0x40b9, 0x0000, 0x3000		// NEGX.L ($3000).L
 	});
+	self.machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend;
+	});
 	*self.machine->ram_at(0x3000) = 0xf001;
 	*self.machine->ram_at(0x3002) = 0x2311;
-	auto state = self.machine->get_processor_state();
-	state.status |= Flag::Extend;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(28, self.machine->get_cycle_count());
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x0ffe);
 	XCTAssertEqual(*self.machine->ram_at(0x3002), 0xdcee);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 }
 
 @end
@@ -1395,10 +1380,9 @@
 	self.machine->set_program({
 		0x0402, value		// SUB.b #value, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = d2;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = d2;
+	});
 	self.machine->run_for_instructions(1);
 
 	XCTAssertEqual(8, self.machine->get_cycle_count());
@@ -1408,50 +1392,48 @@
 	[self performSUBbIMM:0xff d2:0x9ae];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x9af);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x9af);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Extend);
 }
 
 - (void)testSUBb_IMM_82 {
 	[self performSUBbIMM:0x82 d2:0x0a];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x88);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative | Flag::Overflow | Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x88);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Extend);
 }
 
 - (void)testSUBb_IMM_f0 {
 	[self performSUBbIMM:0xf0 d2:0x64];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x74);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[2], 0x74);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testSUBb_IMM_28 {
 	[self performSUBbIMM:0x28 d2:0xff96];
 
 	const auto state = self.machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0xff6e);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow);
+	XCTAssertEqual(state.registers.data[2], 0xff6e);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow);
 }
 
 - (void)testSUBb_PreDec {
 	self.machine->set_program({
 		0x9427		// SUB.b -(A7), D2
+	}, 0x2002);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0x9c40;
 	});
-	self.machine->set_initial_stack_pointer(0x2002);
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x9c40;
 	*self.machine->ram_at(0x2000) = 0x2710;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(10, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], 0x9c19);
-	XCTAssertEqual(state.stack_pointer(), 0x2000);
+	XCTAssertEqual(state.registers.data[2], 0x9c19);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2000);
 }
 
 // Omitted: SUB.w -(A6), D2, which is designed to trigger an address error.
@@ -1460,17 +1442,16 @@
 	self.machine->set_program({
 		0x9578, 0x3000		// SUB.w D2, ($3000).w
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x2711;
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0x2711;
+	});
 	*self.machine->ram_at(0x3000) = 0x759f;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], 0x2711);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[2], 0x2711);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0x4e8e);
 }
 
@@ -1478,20 +1459,19 @@
 	self.machine->set_program({
 		0x95ab, 0x0004		// SUB.l D2, 4(A3)
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[2] = 0x45fd5ab4;
-	state.address[3] = 0x3000;
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[2] = 0x45fd5ab4;
+		registers.address[3] = 0x3000;
+	});
 	*self.machine->ram_at(0x3004) = 0x327a;
 	*self.machine->ram_at(0x3006) = 0x4ef3;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(24, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], 0x45fd5ab4);
-	XCTAssertEqual(state.address[3], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[2], 0x45fd5ab4);
+	XCTAssertEqual(state.registers.address[3], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(*self.machine->ram_at(0x3004), 0xec7c);
 	XCTAssertEqual(*self.machine->ram_at(0x3006), 0xf43f);
 }
@@ -1508,67 +1488,63 @@
 	self.machine->set_program({
 		0x95fc, 0x1234, 0x5678		// SUBA.l #$12345678, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-	state.status |= Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xae43ab1d;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0x9c0f54a5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.address[2], 0x9c0f54a5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testSUBAw_ImmPositive {
 	self.machine->set_program({
 		0x94fc, 0x5678		// SUBA.w #$5678, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xae43ab1d;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(12, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0xae4354a5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0xae4354a5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSUBAw_ImmNegative {
 	self.machine->set_program({
 		0x94fc, 0xf678		// SUBA.w #$5678, A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[2] = 0xae43ab1d;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xae43ab1d;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(12, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0xae43b4a5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0xae43b4a5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSUBAw_PreDec {
 	self.machine->set_program({
 		0x95e2		// SUBA.l -(A2), A2
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[2] = 0x2004;
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0x2004;
+	});
 	*self.machine->ram_at(0x2000) = 0x7002;
 	*self.machine->ram_at(0x2002) = 0x0000;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[2], 0x8ffe2000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[2], 0x8ffe2000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 @end
@@ -1583,16 +1559,15 @@
 	self.machine->set_program({
 		0x0481, 0xf111, 0x1111		// SUBI.L #$f1111111, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x300021b3;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x300021b3;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0x3eef10a2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.data[1], 0x3eef10a2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 // Test of SUBI.W #$7aaa, ($3000).W omitted; that doesn't appear to be a valid instruction?
@@ -1609,32 +1584,30 @@
 	self.machine->set_program({
 		0x5f81		// SUBQ.L #$7, D1
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0xffffffff;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xffffffff;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(8, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0xfffffff8);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0xfffffff8);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 }
 
 - (void)testSUBQw {
 	self.machine->set_program({
 		0x5f49		// SUBQ.W #$7, A1
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[1] = 0xffff0001;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0xffff0001;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(8, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[1], 0xfffefffa);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[1], 0xfffefffa);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSUBQb {
@@ -1648,7 +1621,7 @@
 	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(16, self.machine->get_cycle_count());
 	XCTAssertEqual(*self.machine->ram_at(0x3000), 0xff00);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 }
 
 @end
@@ -1663,58 +1636,55 @@
 	self.machine->set_program({
 		0x9581		// SUBX.l D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x12345678;
-	state.data[2] = 0x12345678;
-	state.status |= Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x12345678;
+		registers.data[2] = 0x12345678;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(8, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 - (void)testSUBXb_Dn {
 	self.machine->set_program({
 		0x9501		// SUBX.b D1, D2
 	});
-	auto state = self.machine->get_processor_state();
-	state.data[1] = 0x80;
-	state.data[2] = 0x01;
-
-	self.machine->set_processor_state(state);
+	self.machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x80;
+		registers.data[2] = 0x01;
+	});
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(4, self.machine->get_cycle_count());
-	XCTAssertEqual(state.data[1], 0x80);
-	XCTAssertEqual(state.data[2], 0x81);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x80);
+	XCTAssertEqual(state.registers.data[2], 0x81);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative | ConditionCode::Overflow);
 }
 
 - (void)testSUBXl_PreDec {
 	self.machine->set_program({
 		0x9389		// SUBX.l -(A1), -(A1)
 	});
-	auto state = self.machine->get_processor_state();
-	state.address[1] = 0x3000;
+	self.machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	*self.machine->ram_at(0x2ff8) = 0x1000;
 	*self.machine->ram_at(0x2ffa) = 0x0000;
 	*self.machine->ram_at(0x2ffc) = 0x7000;
 	*self.machine->ram_at(0x2ffe) = 0x1ff1;
-	state.status |= Flag::ConditionCodes;
-
-	self.machine->set_processor_state(state);
 	self.machine->run_for_instructions(1);
 
-	state = self.machine->get_processor_state();
+	const auto state = self.machine->get_processor_state();
 	XCTAssertEqual(30, self.machine->get_cycle_count());
-	XCTAssertEqual(state.address[1], 0x2ff8);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative );
+	XCTAssertEqual(state.registers.address[1], 0x2ff8);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative );
 	XCTAssertEqual(*self.machine->ram_at(0x2ff8), 0x9fff);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffa), 0xe00e);
 	XCTAssertEqual(*self.machine->ram_at(0x2ffc), 0x7000);
diff --git a/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm b/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm
index 1768a0195..6396cc318 100644
--- a/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000BCDTests.mm	
@@ -32,105 +32,104 @@
 	_machine->set_program({
 		0xc302,		// ABCD D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x1234567a;
-	state.data[2] = 0xf745ff78;
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x1234567a;
+		registers.data[2] = 0xf745ff78;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssertEqual(state.data[1], 0x12345658);
-	XCTAssertEqual(state.data[2], 0xf745ff78);
+	const auto state = _machine->get_processor_state();
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x12345658);
+	XCTAssertEqual(state.registers.data[2], 0xf745ff78);
 }
 
 - (void)testABCDZero {
 	_machine->set_program({
 		0xc302,		// ABCD D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345600;
-	state.data[2] = 0x12345600;
-	state.status = Flag::Zero;
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x12345600;
+		registers.data[2] = 0x12345600;
+		registers.status = ConditionCode::Zero;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Zero);
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.data[2], 0x12345600);
+	const auto state = _machine->get_processor_state();
+	XCTAssert(state.registers.status & ConditionCode::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.data[2], 0x12345600);
 }
 
 - (void)testABCDNegative {
 	_machine->set_program({
 		0xc302,		// ABCD D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345645;
-	state.data[2] = 0x12345654;
-	state.status = Flag::Zero;
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x12345645;
+		registers.data[2] = 0x12345654;
+		registers.status = ConditionCode::Zero;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Negative);
-	XCTAssertEqual(state.data[1], 0x12345699);
-	XCTAssertEqual(state.data[2], 0x12345654);
+	const auto state = _machine->get_processor_state();
+	XCTAssert(state.registers.status & ConditionCode::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x12345699);
+	XCTAssertEqual(state.registers.data[2], 0x12345654);
 }
 
 - (void)testABCDWithX {
 	_machine->set_program({
 		0xc302,		// ABCD D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345645;
-	state.data[2] = 0x12345654;
-	state.status = Flag::Extend;
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x12345645;
+		registers.data[2] = 0x12345654;
+		registers.status = ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.data[2], 0x12345654);
+	const auto state = _machine->get_processor_state();
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.data[2], 0x12345654);
 }
 
 - (void)testABCDOverflow {
 	_machine->set_program({
 		0xc302,		// ABCD D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x1234563e;
-	state.data[2] = 0x1234563e;
-	state.status = Flag::Extend;
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x1234563e;
+		registers.data[2] = 0x1234563e;
+		registers.status = ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Overflow);
-	XCTAssertEqual(state.data[1], 0x12345683);
-	XCTAssertEqual(state.data[2], 0x1234563e);
+	const auto state = _machine->get_processor_state();
+	XCTAssert(state.registers.status & ConditionCode::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x12345683);
+	XCTAssertEqual(state.registers.data[2], 0x1234563e);
 }
 
 - (void)testABCDPredecDifferent {
 	_machine->set_program({
 		0xc30a,		// ABCD -(A2), -(A1)
 	});
+	_machine->set_registers([=](auto &registers){
+		registers.address[1] = 0x3001;
+		registers.address[2] = 0x4001;
+		registers.status = ConditionCode::Extend;
+	});
 	*_machine->ram_at(0x3000) = 0xa200;
 	*_machine->ram_at(0x4000) = 0x1900;
-
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3001;
-	state.address[2] = 0x4001;
-	state.status = Flag::Extend;
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssert(state.status & Flag::Extend);
-	XCTAssertEqual(state.address[1], 0x3000);
-	XCTAssertEqual(state.address[2], 0x4000);
+	const auto state = _machine->get_processor_state();
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssert(state.registers.status & ConditionCode::Extend);
+	XCTAssertEqual(state.registers.address[1], 0x3000);
+	XCTAssertEqual(state.registers.address[2], 0x4000);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x2200);
 	XCTAssertEqual(*_machine->ram_at(0x4000), 0x1900);
 }
@@ -139,18 +138,17 @@
 	_machine->set_program({
 		0xc309,		// ABCD -(A1), -(A1)
 	});
+	_machine->set_registers([=](auto &registers){
+		registers.address[1] = 0x3002;
+		registers.status = ConditionCode::Extend;
+	});
 	*_machine->ram_at(0x3000) = 0x19a2;
-
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3002;
-	state.status = Flag::Extend;
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssert(state.status & Flag::Carry);
-	XCTAssert(state.status & Flag::Extend);
-	XCTAssertEqual(state.address[1], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssert(state.registers.status & ConditionCode::Carry);
+	XCTAssert(state.registers.status & ConditionCode::Extend);
+	XCTAssertEqual(state.registers.address[1], 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x22a2);
 }
 
@@ -160,11 +158,10 @@
 	_machine->set_program({
 		0x4801		// NBCD D1
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= ccr;
-	state.data[1] = d1;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.status |= ccr;
+		registers.data[1] = d1;
+	});
 	_machine->run_for_instructions(1);
 
 	XCTAssertEqual(6, _machine->get_cycle_count());
@@ -174,32 +171,32 @@
 	[self performNBCDd1:0x7a ccr:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 }
 
 - (void)testNBCD_Dn_extend {
-	[self performNBCDd1:0x1234567a ccr:Flag::Extend | Flag::Zero];
+	[self performNBCDd1:0x1234567a ccr:ConditionCode::Extend | ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234561f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x1234561f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 }
 
 - (void)testNBCD_Dn_zero {
-	[self performNBCDd1:0x12345600 ccr:Flag::Zero];
+	[self performNBCDd1:0x12345600 ccr:ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testNBCD_Dn_negative {
-	[self performNBCDd1:0x123456ff ccr:Flag::Extend | Flag::Zero];
+	[self performNBCDd1:0x123456ff ccr:ConditionCode::Extend | ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234569a);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x1234569a);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 - (void)testNBCD_Dn_XXXw {
@@ -213,7 +210,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(16, _machine->get_cycle_count());
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x9900);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 // MARK: SBCD
@@ -222,49 +219,48 @@
 	_machine->set_program({
 		0x8302		// SBCD D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= ccr;
-	state.data[1] = d1;
-	state.data[2] = d2;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.status |= ccr;
+		registers.data[1] = d1;
+		registers.data[2] = d2;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(6, _machine->get_cycle_count());
-	XCTAssertEqual(state.data[2], d2);
+	XCTAssertEqual(state.registers.data[2], d2);
 }
 
 - (void)testSBCD_Dn {
-	[self performSBCDd1:0x12345689 d2:0xf745ff78 ccr:Flag::Zero];
+	[self performSBCDd1:0x12345689 d2:0xf745ff78 ccr:ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345611);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[1], 0x12345611);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testSBCD_Dn_zero {
-	[self performSBCDd1:0x123456ff d2:0xf745ffff ccr:Flag::Zero];
+	[self performSBCDd1:0x123456ff d2:0xf745ffff ccr:ConditionCode::Zero];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[1], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testSBCD_Dn_negative {
-	[self performSBCDd1:0x12345634 d2:0xf745ff45 ccr:Flag::Extend];
+	[self performSBCDd1:0x12345634 d2:0xf745ff45 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345688);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[1], 0x12345688);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Negative);
 }
 
 - (void)testSBCD_Dn_overflow {
-	[self performSBCDd1:0x123456a9 d2:0xf745ffff ccr:Flag::Extend];
+	[self performSBCDd1:0x123456a9 d2:0xf745ffff ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345643);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Overflow);
+	XCTAssertEqual(state.registers.data[1], 0x12345643);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow);
 }
 
 - (void)testSBCD_Dn_PreDec {
@@ -273,19 +269,18 @@
 	});
 	*_machine->ram_at(0x3000) = 0xa200;
 	*_machine->ram_at(0x4000) = 0x1900;
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3001;
-	state.address[2] = 0x4001;
-	state.status |= Flag::Extend;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.address[1] = 0x3001;
+		registers.address[2] = 0x4001;
+		registers.status |= ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(18, _machine->get_cycle_count());
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x8200);
 	XCTAssertEqual(*_machine->ram_at(0x4000), 0x1900);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 }
 
 @end
diff --git a/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm b/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm
index 51bea342f..b4a328994 100644
--- a/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000BitwiseTests.mm	
@@ -32,17 +32,16 @@
 	_machine->set_program({
 		0xc604		// AND.b D4, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54ff7856;
-	state.data[4] = 0x9853abcd;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54ff7856;
+		registers.data[4] = 0x9853abcd;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff7844);
-	XCTAssertEqual(state.data[4], 0x9853abcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54ff7844);
+	XCTAssertEqual(state.registers.data[4], 0x9853abcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 4);
 }
 
@@ -50,17 +49,17 @@
 	_machine->set_program({
 		0xc644		// AND.w D4, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[4] = 0x9853fbcd;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.data[4] = 0x9853fbcd;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff844);
-	XCTAssertEqual(state.data[4], 0x9853fbcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff844);
+	XCTAssertEqual(state.registers.data[4], 0x9853fbcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(_machine->get_cycle_count(), 4);
 }
 
@@ -68,17 +67,16 @@
 	_machine->set_program({
 		0xc684		// AND.l D4, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[4] = 0x9853fbcd;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.data[4] = 0x9853fbcd;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x1053f844);
-	XCTAssertEqual(state.data[4], 0x9853fbcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x1053f844);
+	XCTAssertEqual(state.registers.data[4], 0x9853fbcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -86,27 +84,26 @@
 	_machine->set_program({
 		opcode
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb00);
-	XCTAssertEqual(state.address[4], 0x3000);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
 }
 
 - (void)testANDb_Ind {
 	[self performANDx_Ind:0xc614];	// AND.b (A4), D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff800);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[3], 0x54fff800);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -114,8 +111,8 @@
 	[self performANDx_Ind:0xc654];	// AND.w (A4), D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0052);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54ff0052);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -123,8 +120,8 @@
 	[self performANDx_Ind:0xc694];	// AND.l (A4), D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x0053f800);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x0053f800);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 14);
 }
 
@@ -132,13 +129,13 @@
 	_machine->set_program({
 		opcode		// AND.B (A4)+, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 }
 
@@ -146,29 +143,27 @@
 	[self performANDx_PostInc:0xc61c]; // AND.B (A4)+, D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff800);
-	XCTAssertEqual(state.address[4], 0x3001);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[3], 0x54fff800);
+	XCTAssertEqual(state.registers.address[4], 0x3001);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
 - (void)testANDb_PostInc_A7 {
 	_machine->set_program({
 		0xc61f		// AND.B (A7)+, D3
+	}, 0x3000);
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
 	});
-	_machine->set_initial_stack_pointer(0x3000);
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff800);
-	XCTAssertEqual(state.stack_pointer(), 0x3002);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff800);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x3002);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -176,9 +171,9 @@
 	[self performANDx_PostInc:0xc65c]; // AND.w (A4)+, D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0052);
-	XCTAssertEqual(state.address[4], 0x3002);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x54ff0052);
+	XCTAssertEqual(state.registers.address[4], 0x3002);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -186,9 +181,9 @@
 	[self performANDx_PostInc:0xc69c]; // AND.l (A4)+, D3
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x0053f800);
-	XCTAssertEqual(state.address[4], 0x3004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x0053f800);
+	XCTAssertEqual(state.registers.address[4], 0x3004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 14);
 }
 
@@ -198,21 +193,20 @@
 	_machine->set_program({
 		0xc6a4	// AND.l -(A4), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3004;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3004;
+	});
 	*_machine->ram_at(0x3000) = 0x0053;
 	*_machine->ram_at(0x3002) = 0xfb00;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb00);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.data[3], 0x0053f800);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.data[3], 0x0053f800);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -220,21 +214,20 @@
 	_machine->set_program({
 		0xc6ac, 0xfffa	// AND.l -6(A4), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3006;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3006;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x3006);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3006);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -242,23 +235,22 @@
 	_machine->set_program({
 		0xc6b4, 0x6006	// AND.l 6(A4, D6.W), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[6] = 0xfffffffd;
-	state.address[4] = 0x2ffd;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.data[6] = 0xfffffffd;
+		registers.address[4] = 0x2ffd;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x2ffd);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.data[6], 0xfffffffd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x2ffd);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.data[6], 0xfffffffd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -266,23 +258,22 @@
 	_machine->set_program({
 		0xc6b4, 0x60fe	// AND.l -2(A4, D6.W), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[6] = 0xf001fffd;
-	state.address[4] = 0x3005;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.data[6] = 0xf001fffd;
+		registers.address[4] = 0x3005;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x3005);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.data[6], 0xf001fffd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3005);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.data[6], 0xf001fffd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -290,23 +281,22 @@
 	_machine->set_program({
 		0xc6b4, 0x6801	// AND.l 6(A4, D6.W), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[6] = 0xffffffff;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.data[6] = 0xffffffff;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.data[6], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.data[6], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -314,19 +304,18 @@
 	_machine->set_program({
 		0xc6b8, 0x3000	// AND.l $3000.w, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -334,19 +323,18 @@
 	_machine->set_program({
 		0xc6b9, 0x0001, 0x1170	// AND.L $11170.l, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+	});
 	*_machine->ram_at(0x11170) = 0x1253;
 	*_machine->ram_at(0x11172) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x11170), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x11172), 0xfb34);
-	XCTAssertEqual(state.data[3], 0x1053f814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x1053f814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -354,19 +342,18 @@
 	_machine->set_program({
 		0xc6ba, 0xfffa	// AND.l -6(PC), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+	});
 	*_machine->ram_at(0xffc) = 0x383c;
 	*_machine->ram_at(0xffe) = 0x1234;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0xffc), 0x383c);
 	XCTAssertEqual(*_machine->ram_at(0xffe), 0x1234);
-	XCTAssertEqual(state.data[3], 0x103c1014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x103c1014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -374,20 +361,19 @@
 	_machine->set_program({
 		0xc6bb, 0x10f6	// and.l -10(PC), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.data[1] = 4;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.data[1] = 4;
+	});
 	*_machine->ram_at(0xffc) = 0x383c;
 	*_machine->ram_at(0xffe) = 0x1234;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0xffc), 0x383c);
 	XCTAssertEqual(*_machine->ram_at(0xffe), 0x1234);
-	XCTAssertEqual(state.data[3], 0x103c1014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[3], 0x103c1014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -395,15 +381,14 @@
 	_machine->set_program({
 		0xc63c, 0x0034	// AND.b #$34, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff814);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff814);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -411,15 +396,14 @@
 	_machine->set_program({
 		0xc67c, 0x1234	// AND.w #$1234, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff1014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54ff1014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -427,15 +411,14 @@
 	_machine->set_program({
 		0xc6bc, 0x3456, 0x1234	// AND.l #$34561234, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x14561014);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x14561014);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -443,19 +426,18 @@
 	_machine->set_program({
 		0xc794	// AND.l D3, (A4)
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb03;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -465,19 +447,18 @@
 	_machine->set_program({
 		0xc79c	// AND.l D3, (A4)+
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb03;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3004);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3004);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -487,19 +468,20 @@
 	_machine->set_program({
 		0xc7a4	// AND.l D3, -(A4)
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x2ffc) = 0x1253;
 	*_machine->ram_at(0x2ffe) = 0xfb03;
 
-	_machine->set_processor_state(state);
+
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x2ffc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x2ffc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x2ffe), 0xf802);
 	XCTAssertEqual(22, _machine->get_cycle_count());
@@ -509,19 +491,18 @@
 	_machine->set_program({
 		0xc7ac, 0x0002	// AND.l D3, 2(A4)
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x3002) = 0x1253;
 	*_machine->ram_at(0x3004) = 0xfb03;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0xf802);
 	XCTAssertEqual(24, _machine->get_cycle_count());
@@ -531,19 +512,18 @@
 	_machine->set_program({
 		0xc7b8, 0x3000	// AND.l D3, ($3000).w
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3000;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3000;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb03;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1053);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xf802);
 	XCTAssertEqual(24, _machine->get_cycle_count());
@@ -555,23 +535,22 @@
 	_machine->set_program({
 		0x0340		// BCHG D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+		registers.data[1] = d1;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testBCHG_D0D1_0 {
 	[self performBCHGD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345679);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345679);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -579,8 +558,8 @@
 	[self performBCHGD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345278);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345278);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -588,8 +567,8 @@
 	[self performBCHGD0D1:48];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12355678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12355678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -597,17 +576,16 @@
 	_machine->set_program({
 		0x0350		// BCHG D1, (A0)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	_machine->set_registers([=](auto &registers){
+		registers.address[0] = 0x3000;
+		registers.data[1] = d1;
+	});
 	*_machine->ram_at(0x3000) = 0x7800;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -615,7 +593,7 @@
 	[self performBCHGD1Ind:48];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7900);
 }
 
@@ -623,7 +601,7 @@
 	[self performBCHGD1Ind:7];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xf800);
 }
 
@@ -631,10 +609,9 @@
 	_machine->set_program({
 		0x0840, immediate		// BCHG #, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 }
 
@@ -642,8 +619,8 @@
 	[self performBCHGImm:31];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x92345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x92345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -651,8 +628,8 @@
 	[self performBCHGImm:4];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345668);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345668);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -665,7 +642,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 20);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x3800);
 }
@@ -676,23 +653,22 @@
 	_machine->set_program({
 		0x0380		// BCLR D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+		registers.data[1] = d1;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testBCLR_D0D1_0 {
 	[self performBCLRD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -700,8 +676,8 @@
 	[self performBCLRD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345278);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345278);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -709,8 +685,8 @@
 	[self performBCLRD0D1:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12305678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12305678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -718,17 +694,16 @@
 	_machine->set_program({
 		0x0390		// BCLR D1, (A0)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	_machine->set_registers([=](auto &registers){
+		registers.address[0] = 0x3000;
+		registers.data[1] = d1;
+	});
 	*_machine->ram_at(0x3000) = 0x7800;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -736,7 +711,7 @@
 	[self performBCLRD1Ind:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
 
@@ -744,7 +719,7 @@
 	[self performBCLRD1Ind:3];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7000);
 }
 
@@ -752,21 +727,20 @@
 	_machine->set_program({
 		0x0880, immediate		// BCLR #, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testBCLR_Imm_28 {
 	[self performBCLRImm:28];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x02345678);
+	XCTAssertEqual(state.registers.data[0], 0x02345678);
 	XCTAssertEqual(_machine->get_cycle_count(), 14);
 }
 
@@ -774,7 +748,7 @@
 	[self performBCLRImm:4];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345668);
+	XCTAssertEqual(state.registers.data[0], 0x12345668);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -787,7 +761,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 20);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x3800);
 }
@@ -798,23 +772,22 @@
 	_machine->set_program({
 		0x03c0		// BSET D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+		registers.data[1] = d1;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testBSET_D0D1_0 {
 	[self performBSETD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345679);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12345679);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -822,8 +795,8 @@
 	[self performBSETD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 6);
 }
 
@@ -831,8 +804,8 @@
 	[self performBSETD0D1:49];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12365678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x12365678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -840,17 +813,16 @@
 	_machine->set_program({
 		0x03d0		// BSET D1, (A0)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	_machine->set_registers([=](auto &registers){
+		registers.address[0] = 0x3000;
+		registers.data[1] = d1;
+	});
 	*_machine->ram_at(0x3000) = 0x7800;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -858,7 +830,7 @@
 	[self performBSETD1Ind:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7c00);
 }
 
@@ -866,7 +838,7 @@
 	[self performBSETD1Ind:3];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
 
@@ -874,10 +846,9 @@
 	_machine->set_program({
 		0x08c0, immediate		// BSET #, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 }
 
@@ -885,8 +856,8 @@
 	[self performBSETImm:28];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -894,8 +865,8 @@
 	[self performBSETImm:2];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1234567c);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.data[0], 0x1234567c);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -908,7 +879,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 20);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
@@ -919,16 +890,15 @@
 	_machine->set_program({
 		0x0300		// BTST D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.data[1] = d1;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+		registers.data[1] = d1;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.data[1], d1);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.data[1], d1);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -936,38 +906,37 @@
 	[self performBTSTD0D1:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testBTST_D0D1_10 {
 	[self performBTSTD0D1:10];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testBTST_D0D1_49 {
 	[self performBTSTD0D1:49];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)performBTSTD1Ind:(uint32_t)d1 {
 	_machine->set_program({
 		0x0310		// BTST D1, (A0)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
-	state.data[1] = d1;
+	_machine->set_registers([=](auto &registers){
+		registers.address[0] = 0x3000;
+		registers.data[1] = d1;
+	});
 	*_machine->ram_at(0x3000) = 0x7800;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.address[0], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.address[0], 0x3000);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
@@ -976,28 +945,27 @@
 	[self performBTSTD1Ind:50];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testBTST_D1Ind_3 {
 	[self performBTSTD1Ind:3];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)performBTSTImm:(uint16_t)immediate {
 	_machine->set_program({
 		0x0800, immediate		// BTST #, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345678);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -1005,14 +973,14 @@
 	[self performBTSTImm:28];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)testBTST_Imm_2 {
 	[self performBTSTImm:2];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 - (void)testBTST_ImmWWWx {
@@ -1024,7 +992,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(_machine->get_cycle_count(), 16);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x7800);
 }
@@ -1036,16 +1004,14 @@
 	_machine->set_program({
 		0x0201, 0x0012		// ANDI.B #$12, D1
 	});
-
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345610);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x12345610);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -1062,7 +1028,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(32, _machine->get_cycle_count());
 }
 
@@ -1072,14 +1038,13 @@
 	_machine->set_program({
 		0x023c, 0x001b		// ANDI.b #$1b, CCR
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= 0xc;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.status |= 0xc;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0xc & 0x1b);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0xc & 0x1b);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1088,13 +1053,12 @@
 - (void)testANDISR_supervisor {
 	_machine->set_program({
 		0x027c, 0x0700		// ANDI.W #$700, SR
-	});
-	_machine->set_initial_stack_pointer(300);
+	}, 300);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1107,7 +1071,7 @@
 	_machine->run_for_instructions(2);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1008 + 4);
 //	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -1117,18 +1081,16 @@
 	_machine->set_program({
 		0xb744		// EOR.w D3, D4
 	});
-
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[3] = 0x54ff0056;
-	state.data[4] = 0x9853abcd;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+		registers.data[3] = 0x54ff0056;
+		registers.data[4] = 0x9853abcd;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0056);
-	XCTAssertEqual(state.data[4], 0x9853ab9b);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54ff0056);
+	XCTAssertEqual(state.registers.data[4], 0x9853ab9b);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1136,22 +1098,20 @@
 	_machine->set_program({
 		0xb792		// EOR.l D3, (A2)
 	});
-
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
-	state.data[3] = 0x54ff0056;
+	_machine->set_registers([=](auto &registers){
+		registers.address[2] = 0x3000;
+		registers.data[3] = 0x54ff0056;
+	});
 	*_machine->ram_at(0x3000) = 0x0f0f;
 	*_machine->ram_at(0x3002) = 0x0f11;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff0056);
-	XCTAssertEqual(state.address[2], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54ff0056);
+	XCTAssertEqual(state.registers.address[2], 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x5bf0);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0f47);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1161,16 +1121,14 @@
 	_machine->set_program({
 		0x0a01, 0x0012		// EORI.B #$12, D1
 	});
-
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234566a);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x1234566a);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -1187,7 +1145,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xffff);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(32, _machine->get_cycle_count());
 }
 
@@ -1198,14 +1156,13 @@
 		0x0a3c, 0x001b		// EORI.b #$1b, CCR
 	});
 
-	auto state = _machine->get_processor_state();
-	state.status |= 0xc;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.status |= 0xc;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0xc ^ 0x1b);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0xc ^ 0x1b);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1214,13 +1171,12 @@
 - (void)testEORISR_supervisor {
 	_machine->set_program({
 		0x0a7c, 0x0700		// EORI.W #$700, SR
-	});
-	_machine->set_initial_stack_pointer(300);
+	}, 300);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1233,7 +1189,7 @@
 	_machine->run_for_instructions(2);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1008 + 4);
 //	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -1243,15 +1199,14 @@
 	_machine->set_program({
 		0x4600		// NOT.B D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345687);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x12345687);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1259,16 +1214,15 @@
 	_machine->set_program({
 		0x4640		// NOT.w D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12340000;
-	state.status |= Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0x12340000;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1234ffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x1234ffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1276,16 +1230,15 @@
 	_machine->set_program({
 		0x4680		// NOT.l D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xffffff00;
-	state.status |= Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = 0xffffff00;
+		registers.status |= ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x000000ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x000000ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -1293,18 +1246,17 @@
 	_machine->set_program({
 		0x46b9, 0x0000, 0x3000		// NOT.L ($3000).L
 	});
+	_machine->set_registers([=](auto &registers){
+		registers.status |= ConditionCode::Extend;
+	});
 	*_machine->ram_at(0x3000) = 0xf001;
 	*_machine->ram_at(0x3002) = 0x2311;
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x0ffe);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xdcee);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -1314,18 +1266,17 @@
 	_machine->set_program({
 		0x8604		// OR.b D4, D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54ff0056;
-	state.data[4] = 0x9853abcd;
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54ff0056;
+		registers.data[4] = 0x9853abcd;
+		registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54ff00df);
-	XCTAssertEqual(state.data[4], 0x9853abcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54ff00df);
+	XCTAssertEqual(state.registers.data[4], 0x9853abcd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1333,21 +1284,20 @@
 	_machine->set_program({
 		0x86ac, 0xfffa		// OR.l -6(A4), D3
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3006;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3006;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x56fffb76);
-	XCTAssertEqual(state.address[4], 0x3006);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x56fffb76);
+	XCTAssertEqual(state.registers.address[4], 0x3006);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1253);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb34);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -1355,21 +1305,20 @@
 	_machine->set_program({
 		0x87ac, 0xfffa		// OR.l D3, -6(A4)
 	});
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x54fff856;
-	state.address[4] = 0x3006;
+	_machine->set_registers([=](auto &registers){
+		registers.data[3] = 0x54fff856;
+		registers.address[4] = 0x3006;
+	});
 	*_machine->ram_at(0x3000) = 0x1253;
 	*_machine->ram_at(0x3002) = 0xfb34;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[3], 0x54fff856);
-	XCTAssertEqual(state.address[4], 0x3006);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[3], 0x54fff856);
+	XCTAssertEqual(state.registers.address[4], 0x3006);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x56ff);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xfb76);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -1379,16 +1328,14 @@
 	_machine->set_program({
 		0x0001, 0x0012		// ORI.B #$12, D1
 	});
-
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[1] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1234567a);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x1234567a);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -1405,7 +1352,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xffff);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(32, _machine->get_cycle_count());
 }
 
@@ -1415,15 +1362,13 @@
 	_machine->set_program({
 		0x003c, 0x001b		// ORI.b #$1b, CCR
 	});
-
-	auto state = _machine->get_processor_state();
-	state.status |= 0xc;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.status |= 0xc;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0xc | 0x1b);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0xc | 0x1b);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1432,13 +1377,12 @@
 - (void)testORISR_supervisor {
 	_machine->set_program({
 		0x007c, 0x0700		// ORI.W #$700, SR
-	});
-	_machine->set_initial_stack_pointer(300);
+	}, 300);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -1451,7 +1395,7 @@
 	_machine->run_for_instructions(2);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertNotEqual(state.registers.program_counter, 0x1008 + 4);
 //	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -1461,15 +1405,13 @@
 	_machine->set_program({
 		0x4ac0		// TAS D0
 	});
-
-	auto state = _machine->get_processor_state();
-	state.data[0] = d0;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers){
+		registers.data[0] = d0;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, ccr);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ccr);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1478,23 +1420,21 @@
 }
 
 - (void)testTAS_Dn_set {
-	[self performTASDnd0:0x123456f0 expectedCCR:Flag::Negative];
+	[self performTASDnd0:0x123456f0 expectedCCR:ConditionCode::Negative];
 }
 
 - (void)testTAS_XXXl {
 	_machine->set_program({
 		0x4af9, 0x0000, 0x3000		// TAS ($3000).l
 	});
+	_machine->set_registers([=](auto &registers){
+		registers.status |= ConditionCode::AllConditions;
+	});
 	*_machine->ram_at(0x3000) = 0x1100;
-
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x9100);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
diff --git a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm
index 73d0b4bf0..94c6cddce 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ComparativeTests.mm	
@@ -8,7 +8,7 @@
 
 #import <XCTest/XCTest.h>
 
-#include "../../../Processors/68000/68000.hpp"
+#include "../../../Processors/68000Mk2/68000Mk2.hpp"
 #include "../../../InstructionSets/M68k/Executor.hpp"
 #include "../../../InstructionSets/M68k/Decoder.hpp"
 
@@ -16,18 +16,18 @@
 #include <memory>
 #include <functional>
 
-//#define USE_EXISTING_IMPLEMENTATION
+//#define USE_EXECUTOR
 //#define MAKE_SUGGESTIONS
+//#define LOG_UNTESTED
 
 namespace {
 
 /// Binds a 68000 executor to 16mb of RAM.
-struct Test68000 {
-	std::array<uint8_t, 16*1024*1024> ram;
-	InstructionSet::M68k::Executor<InstructionSet::M68k::Model::M68000, Test68000> processor;
+struct TestExecutor {
+	uint8_t *const ram;
+	InstructionSet::M68k::Executor<InstructionSet::M68k::Model::M68000, TestExecutor> processor;
 
-	Test68000() : processor(*this) {
-	}
+	TestExecutor(uint8_t *ram) : ram(ram), processor(*this) {}
 
 	void run_for_instructions(int instructions) {
 		processor.run_for_instructions(instructions);
@@ -83,6 +83,39 @@ struct Test68000 {
 	}
 };
 
+/// Binds a bus-accurate 68000 to 16mb of RAM.
+struct TestProcessor: public CPU::MC68000Mk2::BusHandler {
+	uint8_t *const ram;
+	CPU::MC68000Mk2::Processor<TestProcessor, true, true, true> processor;
+	std::function<void(void)> comparitor;
+
+	TestProcessor(uint8_t *ram) : ram(ram), processor(*this) {}
+
+	void will_perform(uint32_t, uint16_t) {
+		--instructions_remaining_;
+		if(!instructions_remaining_) comparitor();
+	}
+
+	HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
+		using Microcycle = CPU::MC68000Mk2::Microcycle;
+		if(cycle.data_select_active()) {
+			cycle.apply(&ram[cycle.host_endian_byte_address()]);
+		}
+		return HalfCycles(0);
+	}
+
+	void run_for_instructions(int instructions, const std::function<void(void)> &compare) {
+		instructions_remaining_ = instructions + 1;	// i.e. run up to the will_perform of the instruction after.
+		comparitor = std::move(compare);
+		while(instructions_remaining_) {
+			processor.run_for(HalfCycles(2));
+		}
+	}
+
+	private:
+		int instructions_remaining_;
+};
+
 }
 
 @interface M68000ComparativeTests : XCTestCase
@@ -95,23 +128,41 @@ struct Test68000 {
 	NSMutableSet<NSString *> *_failures;
 	NSMutableArray<NSNumber *> *_failingOpcodes;
 	NSMutableDictionary<NSNumber *, NSMutableArray<NSString *> *> *_suggestedCorrections;
+	NSMutableSet<NSNumber *> *_testedOpcodes;
 
 	InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> _decoder;
-	Test68000 _test68000;
+
+	std::array<uint16_t, 8*1024*1024> _ram;
+	std::unique_ptr<TestExecutor> _testExecutor;
 }
 
 - (void)setUp {
+	// Definitively erase any prior memory contents;
+	// 0xce is arbitrary but hopefully easier to spot
+	// in potential errors than e.g. 0x00 or 0xff.
+	_ram.fill(0xcece);
+
+	// TODO: possibly, worry about resetting RAM to 0xce after tests have completed.
+
+#ifdef USE_EXECUTOR
+	_testExecutor = std::make_unique<TestExecutor>(reinterpret_cast<uint8_t *>(_ram.data()));
+#endif
+
 	// These will accumulate a list of failing tests and associated opcodes.
 	_failures = [[NSMutableSet alloc] init];
 	_failingOpcodes = [[NSMutableArray alloc] init];
 
+	// This will simply accumulate a list of all tested opcodes, in order to report
+	// on those that are missing.
+	_testedOpcodes = [[NSMutableSet alloc] init];
+
 #ifdef MAKE_SUGGESTIONS
 	_suggestedCorrections = [[NSMutableDictionary alloc] init];
 #endif
 
 	// To limit tests run to a subset of files and/or of tests, uncomment and fill in below.
-//	_fileSet = [NSSet setWithArray:@[@"exg.json"]];
-//	_testSet = [NSSet setWithArray:@[@"CHK 41a8"]];
+//	_fileSet = [NSSet setWithArray:@[@"abcd_sbcd.json"]];
+//	_testSet = [NSSet setWithArray:@[@"LINK.w 0007"]];
 }
 
 - (void)testAll {
@@ -126,7 +177,7 @@ struct Test68000 {
 //		NSLog(@"Testing %@", url);
 		[self testJSONAtURL:url];
 	}
-
+ 
 	XCTAssert(_failures.count == 0);
 
 	// Output a summary of failures, if any.
@@ -145,6 +196,25 @@ struct Test68000 {
 			}
 		}
 	}
+
+#ifdef LOG_UNTESTED
+	// Output a list of untested opcodes.
+	NSMutableArray<NSString *> *untested = [[NSMutableArray alloc] init];
+	for(int opcode = 0; opcode < 65536; opcode++) {
+		const auto instruction = _decoder.decode(uint16_t(opcode));
+
+		if(instruction.operation == InstructionSet::M68k::Operation::Undefined) {
+			continue;
+		}
+		if([_testedOpcodes containsObject:@(opcode)]) {
+			continue;
+		}
+
+		[untested addObject:[NSString stringWithFormat:@"%04x %s", opcode, instruction.to_string(uint16_t(opcode)).c_str()]];
+	}
+
+	NSLog(@"Untested: %@", untested);
+#endif
 }
 
 - (void)testJSONAtURL:(NSURL *)url {
@@ -153,9 +223,9 @@ struct Test68000 {
 	NSError *error;
 	NSArray *const jsonContents = [NSJSONSerialization JSONObjectWithData:data options:0 error:&error];
 
-	if(!data || error || ![jsonContents isKindOfClass:[NSArray class]]) {
-		return;
-	}
+	XCTAssertNil(error);
+	XCTAssertNotNil(jsonContents);
+	XCTAssert([jsonContents isKindOfClass:[NSArray class]]);
 
 	// Perform each dictionary in the array as a test.
 	for(NSDictionary *test in jsonContents) {
@@ -168,52 +238,33 @@ struct Test68000 {
 		// Compare against a test set if one has been supplied.
 		if(_testSet && ![_testSet containsObject:name]) continue;
 
-#ifdef USE_EXISTING_IMPLEMENTATION
-		[self testOperationClassic:test name:name];
-#else
+		// Pull out the opcode and record it.
+		NSArray<NSNumber *> *const initialMemory = test[@"initial memory"];
+		uint16_t opcode = 0;
+		NSEnumerator<NSNumber *> *enumerator = [initialMemory objectEnumerator];
+		while(true) {
+			NSNumber *const address = [enumerator nextObject];
+			NSNumber *const value = [enumerator nextObject];
+
+			if(!address || !value) break;
+			if(address.integerValue == 0x100) opcode |= value.integerValue << 8;
+			if(address.integerValue == 0x101) opcode |= value.integerValue;
+		}
+		[_testedOpcodes addObject:@(opcode)];
+
+#ifdef USE_EXECUTOR
 		[self testOperationExecutor:test name:name];
+#else
+		[self testOperationClassic:test name:name];
 #endif
 	}
 }
 
 - (void)testOperationClassic:(NSDictionary *)test name:(NSString *)name  {
+	struct TerminateMarker {};
 
-	// This is the test class for 68000 execution.
-	struct Test68000: public CPU::MC68000::BusHandler {
-		std::array<uint8_t, 16*1024*1024> ram;
-		CPU::MC68000::Processor<Test68000, true, true> processor;
-		std::function<void(void)> comparitor;
-
-		Test68000() : processor(*this) {
-		}
-
-		void will_perform(uint32_t, uint16_t) {
-			--instructions_remaining_;
-			if(!instructions_remaining_) comparitor();
-		}
-
-		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
-			using Microcycle = CPU::MC68000::Microcycle;
-			if(cycle.data_select_active()) {
-				cycle.apply(&ram[cycle.host_endian_byte_address()]);
-			}
-			return HalfCycles(0);
-		}
-
-		void run_for_instructions(int instructions, const std::function<void(void)> &compare) {
-			instructions_remaining_ = instructions + 1;	// i.e. run up to the will_perform of the instruction after.
-			comparitor = std::move(compare);
-			while(instructions_remaining_) {
-				processor.run_for(HalfCycles(2));
-			}
-		}
-
-		private:
-			int instructions_remaining_;
-	};
-	auto uniqueTest68000 = std::make_unique<Test68000>();
+	auto uniqueTest68000 = std::make_unique<TestProcessor>(reinterpret_cast<uint8_t *>(_ram.data()));
 	auto test68000 = uniqueTest68000.get();
-	memset(test68000->ram.data(), 0xce, test68000->ram.size());
 
 	{
 		// Apply initial memory state.
@@ -228,47 +279,24 @@ struct Test68000 {
 		}
 
 		// Apply initial processor state.
-		NSDictionary *const initialState = test[@"initial state"];
 		auto state = test68000->processor.get_state();
-		for(int c = 0; c < 8; ++c) {
-			const NSString *dX = [@"d" stringByAppendingFormat:@"%d", c];
-			const NSString *aX = [@"a" stringByAppendingFormat:@"%d", c];
-
-			state.data[c] = uint32_t([initialState[dX] integerValue]);
-			if(c < 7)
-				state.address[c] = uint32_t([initialState[aX] integerValue]);
-		}
-		state.supervisor_stack_pointer = uint32_t([initialState[@"a7"] integerValue]);
-		state.user_stack_pointer = uint32_t([initialState[@"usp"] integerValue]);
-		state.status = [initialState[@"sr"] integerValue];
+		state.registers = [self initialRegisters:test];
 		test68000->processor.set_state(state);
 	}
 
+	// Check that this is a defined opcode; capture of the unrecognised instruction
+	// exception doesn't work correctly with the way that this test class tries
+	// to detect the gaps between operations.
+	const uint16_t opcode = (test68000->ram[0x101] << 8) | test68000->ram[0x100];
+	if(_decoder.decode(opcode).operation == InstructionSet::M68k::Operation::Undefined) {
+		return;
+	}
+
 	// Run the thing.
 	const auto comparitor = [=] {
-		// Test the end state.
-		NSDictionary *const finalState = test[@"final state"];
 		const auto state = test68000->processor.get_state();
-		for(int c = 0; c < 8; ++c) {
-			const NSString *dX = [@"d" stringByAppendingFormat:@"%d", c];
-			const NSString *aX = [@"a" stringByAppendingFormat:@"%d", c];
 
-			if(state.data[c] != [finalState[dX] integerValue]) [_failures addObject:name];
-			if(c < 7 && state.address[c] != [finalState[aX] integerValue]) [_failures addObject:name];
-
-			XCTAssertEqual(state.data[c], [finalState[dX] integerValue], @"%@: D%d inconsistent", name, c);
-			if(c < 7) {
-				XCTAssertEqual(state.address[c], [finalState[aX] integerValue], @"%@: A%d inconsistent", name, c);
-			}
-		}
-		if(state.supervisor_stack_pointer != [finalState[@"a7"] integerValue]) [_failures addObject:name];
-		if(state.user_stack_pointer != [finalState[@"usp"] integerValue]) [_failures addObject:name];
-		if(state.status != [finalState[@"sr"] integerValue]) [_failures addObject:name];
-
-		XCTAssertEqual(state.supervisor_stack_pointer, [finalState[@"a7"] integerValue], @"%@: A7 inconsistent", name);
-		XCTAssertEqual(state.user_stack_pointer, [finalState[@"usp"] integerValue], @"%@: USP inconsistent", name);
-		XCTAssertEqual(state.status, [finalState[@"sr"] integerValue], @"%@: Status inconsistent", name);
-		XCTAssertEqual(state.program_counter - 4, [finalState[@"pc"] integerValue], @"%@: Program counter inconsistent", name);
+		[self test:test name:name compareFinalRegisters:state.registers opcode:opcode pcOffset:-4];
 
 		// Test final memory state.
 		NSArray<NSNumber *> *const finalMemory = test[@"final memory"];
@@ -284,19 +312,19 @@ struct Test68000 {
 
 		// Consider collating extra detail.
 		if([_failures containsObject:name]) {
-			[_failingOpcodes addObject:@((test68000->ram[0x101] << 8) | test68000->ram[0x100])];
+			[_failingOpcodes addObject:@(opcode)];
 		}
+
+		// Make sure nothing further occurs; keep this test isolated.
+		throw TerminateMarker();
 	};
 
-	test68000->run_for_instructions(1, comparitor);
+	try {
+		test68000->run_for_instructions(1, comparitor);
+	} catch(TerminateMarker m) {}
 }
 
 - (void)setInitialState:(NSDictionary *)test {
-	// Definitively erase any prior memory contents;
-	// 0xce is arbitrary but hopefully easier to spot
-	// in potential errors than e.g. 0x00 or 0xff.
-	memset(_test68000.ram.data(), 0xce, _test68000.ram.size());
-
 	// Apply initial memory state.
 	NSArray<NSNumber *> *const initialMemory = test[@"initial memory"];
 	NSEnumerator<NSNumber *> *enumerator = [initialMemory objectEnumerator];
@@ -305,72 +333,23 @@ struct Test68000 {
 		NSNumber *const value = [enumerator nextObject];
 
 		if(!address || !value) break;
-		_test68000.ram[address.integerValue] = value.integerValue;
+		_testExecutor->ram[address.integerValue] = value.integerValue;
 	}
 
 	// Apply initial processor state.
-	NSDictionary *const initialState = test[@"initial state"];
-	auto state = _test68000.processor.get_state();
-	for(int c = 0; c < 8; ++c) {
-		const NSString *dX = [@"d" stringByAppendingFormat:@"%d", c];
-		const NSString *aX = [@"a" stringByAppendingFormat:@"%d", c];
-
-		state.data[c] = uint32_t([initialState[dX] integerValue]);
-		if(c < 7)
-			state.address[c] = uint32_t([initialState[aX] integerValue]);
-	}
-	state.supervisor_stack_pointer = uint32_t([initialState[@"a7"] integerValue]);
-	state.user_stack_pointer = uint32_t([initialState[@"usp"] integerValue]);
-	state.status = [initialState[@"sr"] integerValue];
-	state.program_counter = uint32_t([initialState[@"pc"] integerValue]);
-	_test68000.processor.set_state(state);
+	_testExecutor->processor.set_state([self initialRegisters:test]);
 }
 
 - (void)testOperationExecutor:(NSDictionary *)test name:(NSString *)name {
 	[self setInitialState:test];
 
 	// Run the thing.
-	_test68000.run_for_instructions(1);
+	_testExecutor->run_for_instructions(1);
 
 	// Test the end state.
-	NSDictionary *const finalState = test[@"final state"];
-	const auto state = _test68000.processor.get_state();
-	for(int c = 0; c < 8; ++c) {
-		const NSString *dX = [@"d" stringByAppendingFormat:@"%d", c];
-		const NSString *aX = [@"a" stringByAppendingFormat:@"%d", c];
-
-		if(state.data[c] != [finalState[dX] integerValue]) [_failures addObject:name];
-		if(c < 7 && state.address[c] != [finalState[aX] integerValue]) [_failures addObject:name];
-	}
-	if(state.supervisor_stack_pointer != [finalState[@"a7"] integerValue]) [_failures addObject:name];
-	if(state.user_stack_pointer != [finalState[@"usp"] integerValue]) [_failures addObject:name];
-
-	const uint16_t correctSR = [finalState[@"sr"] integerValue];
-	if(state.status != correctSR) {
-		const uint16_t opcode = _test68000.read<uint16_t>(0x100, InstructionSet::M68k::FunctionCode());
-		const auto instruction = _decoder.decode(opcode);
-
-		// For DIVU and DIVS, for now, test only the well-defined flags.
-		if(
-			instruction.operation != InstructionSet::M68k::Operation::DIVS &&
-			instruction.operation != InstructionSet::M68k::Operation::DIVU
-		) {
-			[_failures addObject:name];
-		} else {
-			uint16_t status_mask = 0xff13;	// i.e. extend, which should be unaffected, and overflow, which
-											// is well-defined unless there was a divide by zero. But this
-											// test set doesn't include any divide by zeroes.
-
-			if(!(correctSR & InstructionSet::M68k::ConditionCode::Overflow)) {
-				// If overflow didn't occur then negative and zero are also well-defined.
-				status_mask |= 0x000c;
-			}
-
-			if((state.status & status_mask) != (([finalState[@"sr"] integerValue]) & status_mask)) {
-				[_failures addObject:name];
-			}
-		}
-	}
+	const auto state = _testExecutor->processor.get_state();
+	const uint16_t opcode = _testExecutor->read<uint16_t>(0x100, InstructionSet::M68k::FunctionCode());
+	[self test:test name:name compareFinalRegisters:state opcode:opcode pcOffset:0];
 
 	// Test final memory state.
 	NSArray<NSNumber *> *const finalMemory = test[@"final memory"];
@@ -380,16 +359,14 @@ struct Test68000 {
 		NSNumber *const value = [enumerator nextObject];
 
 		if(!address || !value) break;
-		if(_test68000.ram[address.integerValue] != value.integerValue) [_failures addObject:name];
+		if(_testExecutor->ram[address.integerValue] != value.integerValue) [_failures addObject:name];
 	}
 
 	// If this test is now in the failures set, add the corresponding opcode for
 	// later logging.
 	if([_failures containsObject:name]) {
-		NSNumber *const opcode = @(_test68000.read<uint16_t>(0x100, InstructionSet::M68k::FunctionCode()));
-
 		// Add this opcode to the failing list.
-		[_failingOpcodes addObject:opcode];
+		[_failingOpcodes addObject:@(opcode)];
 
 		// Generate the JSON that would have satisfied this test, at least as far as registers go,
 		// if those are being collected.
@@ -412,10 +389,71 @@ struct Test68000 {
 						[NSJSONSerialization dataWithJSONObject:generatedTest options:0 error:nil]
 						encoding:NSUTF8StringEncoding];
 
-			if(_suggestedCorrections[opcode]) {
-				[_suggestedCorrections[opcode] addObject:generatedJSON];
+			if(_suggestedCorrections[@(opcode)]) {
+				[_suggestedCorrections[@(opcode)] addObject:generatedJSON];
 			} else {
-				_suggestedCorrections[opcode] = [NSMutableArray arrayWithObject:generatedJSON];
+				_suggestedCorrections[@(opcode)] = [NSMutableArray arrayWithObject:generatedJSON];
+			}
+		}
+	}
+}
+
+- (InstructionSet::M68k::RegisterSet)initialRegisters:(NSDictionary *)test {
+	InstructionSet::M68k::RegisterSet registers;
+
+	NSDictionary *const initialState = test[@"initial state"];
+	for(int c = 0; c < 8; ++c) {
+		const NSString *dX = [@"d" stringByAppendingFormat:@"%d", c];
+		const NSString *aX = [@"a" stringByAppendingFormat:@"%d", c];
+
+		registers.data[c] = uint32_t([initialState[dX] integerValue]);
+		if(c < 7)
+			registers.address[c] = uint32_t([initialState[aX] integerValue]);
+	}
+	registers.supervisor_stack_pointer = uint32_t([initialState[@"a7"] integerValue]);
+	registers.user_stack_pointer = uint32_t([initialState[@"usp"] integerValue]);
+	registers.status = [initialState[@"sr"] integerValue];
+	registers.program_counter = uint32_t([initialState[@"pc"] integerValue]);
+
+	return registers;
+}
+
+- (void)test:(NSDictionary *)test name:(NSString *)name compareFinalRegisters:(InstructionSet::M68k::RegisterSet)registers opcode:(uint16_t)opcode pcOffset:(int)pcOffset {
+	// Test the end state.
+	NSDictionary *const finalState = test[@"final state"];
+	for(int c = 0; c < 8; ++c) {
+		const NSString *dX = [@"d" stringByAppendingFormat:@"%d", c];
+		const NSString *aX = [@"a" stringByAppendingFormat:@"%d", c];
+
+		if(registers.data[c] != [finalState[dX] integerValue]) [_failures addObject:name];
+		if(c < 7 && registers.address[c] != [finalState[aX] integerValue]) [_failures addObject:name];
+	}
+	if(registers.supervisor_stack_pointer != [finalState[@"a7"] integerValue]) [_failures addObject:name];
+	if(registers.user_stack_pointer != [finalState[@"usp"] integerValue]) [_failures addObject:name];
+	if(registers.program_counter + pcOffset != [finalState[@"pc"] integerValue]) [_failures addObject:name];
+
+	const uint16_t correctSR = [finalState[@"sr"] integerValue];
+	if(registers.status != correctSR) {
+		const auto instruction = _decoder.decode(opcode);
+
+		// For DIVU and DIVS, for now, test only the well-defined flags.
+		if(
+			instruction.operation != InstructionSet::M68k::Operation::DIVS &&
+			instruction.operation != InstructionSet::M68k::Operation::DIVU
+		) {
+			[_failures addObject:name];
+		} else {
+			uint16_t status_mask = 0xff13;	// i.e. extend, which should be unaffected, and overflow, which
+											// is well-defined unless there was a divide by zero. But this
+											// test set doesn't include any divide by zeroes.
+
+			if(!(correctSR & InstructionSet::M68k::ConditionCode::Overflow)) {
+				// If overflow didn't occur then negative and zero are also well-defined.
+				status_mask |= 0x000c;
+			}
+
+			if((registers.status & status_mask) != (([finalState[@"sr"] integerValue]) & status_mask)) {
+				[_failures addObject:name];
 			}
 		}
 	}
diff --git a/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm b/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm
index 947abf8fe..2f8db01fc 100644
--- a/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000ControlFlowTests.mm	
@@ -49,7 +49,7 @@
 	[self performBccb:0x6200];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -57,7 +57,7 @@
 	[self performBccb:0x6500];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 8);
 }
 
@@ -65,7 +65,7 @@
 	[self performBccw:0x6200];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -73,7 +73,7 @@
 	[self performBccw:0x6500];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1004 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1004 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 12);
 }
 
@@ -87,7 +87,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1006 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1006 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -99,7 +99,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1006 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1006 + 4);
 	XCTAssertEqual(_machine->get_cycle_count(), 10);
 }
 
@@ -108,15 +108,14 @@
 - (void)testBSRw {
 	_machine->set_program({
 		0x6100, 0x0006		// BSR.w $1008
-	});
-	_machine->set_initial_stack_pointer(0x3000);
+	}, 0x3000);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
-	XCTAssertEqual(state.stack_pointer(), 0x2ffc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2ffc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffe), 0x1004);
 
@@ -126,15 +125,14 @@
 - (void)testBSRb {
 	_machine->set_program({
 		0x6106		// BSR.b $1008
-	});
-	_machine->set_initial_stack_pointer(0x3000);
+	}, 0x3000);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
-	XCTAssertEqual(state.stack_pointer(), 0x2ffc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2ffc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0);
 	XCTAssertEqual(*_machine->ram_at(0x2ffe), 0x1002);
 
@@ -146,56 +144,61 @@
 - (void)performCHKd1:(uint32_t)d1 d2:(uint32_t)d2 {
 	_machine->set_program({
 		0x4581		// CHK D1, D2
+	}, 0);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = d1;
+		registers.data[2] = d2;
+		registers.status |= ConditionCode::AllConditions;
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = d1;
-	state.data[2] = d2;
-	state.status |= Flag::ConditionCodes;
-
-	_machine->set_initial_stack_pointer(0);
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
-	XCTAssertEqual(state.data[2], d2);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
+	XCTAssertEqual(state.registers.data[2], d2);
 }
 
+// Re: CHK, below; the final state of N is undocumented if Dn >= 0 and Dn < <ea>.
+// Z, V and C are also undocumented by Motorola, but are documneted by 68knotes.txt.
+
 - (void)testCHK_1111v1111 {
-	[self performCHKd1:0x1111 d2:0x1111];
+	[self performCHKd1:0x1111 d2:0x1111];		// Neither exception-generating state applies.
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(
+		state.registers.status & (ConditionCode::Extend | ConditionCode::Zero | ConditionCode::Overflow | ConditionCode::Carry),
+		ConditionCode::Extend);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
 - (void)testCHK_1111v0000 {
-	[self performCHKd1:0x1111 d2:0x0000];
+	[self performCHKd1:0x1111 d2:0x0000];		// Neither exception-generating state applies.
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(
+		state.registers.status & (ConditionCode::Extend | ConditionCode::Zero | ConditionCode::Overflow | ConditionCode::Carry),
+		ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
 - (void)testCHK_8000v8001 {
-	[self performCHKd1:0x8000 d2:0x8001];
+	[self performCHKd1:0x8000 d2:0x8001];		// Both less than 0 and D2 greater than D1.
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.stack_pointer(), 0xfffffffa);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
-	XCTAssertEqual(42, _machine->get_cycle_count());
+	XCTAssertNotEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0xfffffffa);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
+	XCTAssertEqual(38, _machine->get_cycle_count());
 }
 
 - (void)testCHK_8000v8000 {
-	[self performCHKd1:0x8000 d2:0x8000];
+	[self performCHKd1:0x8000 d2:0x8000];		// Less than 0.
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertNotEqual(state.program_counter, 0x1002 + 4);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
-	XCTAssertEqual(44, _machine->get_cycle_count());
+	XCTAssertNotEqual(state.registers.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
+	XCTAssertEqual(40, _machine->get_cycle_count());
 }
 
 // MARK: DBcc
@@ -204,16 +207,15 @@
 	_machine->set_program({
 		opcode, 0x0008		// DBcc D2, +8
 	});
-	auto state = _machine->get_processor_state();
-	state.status = status;
-	state.data[2] = 1;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+			registers.status = status;
+			registers.data[2] = 1;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[2], d2Output);
-	XCTAssertEqual(state.status, status);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[2], d2Output);
+	XCTAssertEqual(state.registers.status, status);
 }
 
 - (void)testDBT {
@@ -229,27 +231,27 @@
 }
 
 - (void)testDBHI_Carry {
-	[self performDBccTestOpcode:0x52ca status:Flag::Carry d2Outcome:0];
+	[self performDBccTestOpcode:0x52ca status:ConditionCode::Carry d2Outcome:0];
 }
 
 - (void)testDBHI_Zero {
-	[self performDBccTestOpcode:0x52ca status:Flag::Zero d2Outcome:0];
+	[self performDBccTestOpcode:0x52ca status:ConditionCode::Zero d2Outcome:0];
 }
 
 - (void)testDBLS_CarryOverflow {
-	[self performDBccTestOpcode:0x53ca status:Flag::Carry | Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x53ca status:ConditionCode::Carry | ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBLS_Carry {
-	[self performDBccTestOpcode:0x53ca status:Flag::Carry d2Outcome:1];
+	[self performDBccTestOpcode:0x53ca status:ConditionCode::Carry d2Outcome:1];
 }
 
 - (void)testDBLS_Overflow {
-	[self performDBccTestOpcode:0x53ca status:Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x53ca status:ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBCC_Carry {
-	[self performDBccTestOpcode:0x54ca status:Flag::Carry d2Outcome:0];
+	[self performDBccTestOpcode:0x54ca status:ConditionCode::Carry d2Outcome:0];
 }
 
 - (void)testDBCC {
@@ -261,7 +263,7 @@
 }
 
 - (void)testDBCS_Carry {
-	[self performDBccTestOpcode:0x55ca status:Flag::Carry d2Outcome:1];
+	[self performDBccTestOpcode:0x55ca status:ConditionCode::Carry d2Outcome:1];
 }
 
 - (void)testDBNE {
@@ -269,7 +271,7 @@
 }
 
 - (void)testDBNE_Zero {
-	[self performDBccTestOpcode:0x56ca status:Flag::Zero d2Outcome:0];
+	[self performDBccTestOpcode:0x56ca status:ConditionCode::Zero d2Outcome:0];
 }
 
 - (void)testDBEQ {
@@ -277,7 +279,7 @@
 }
 
 - (void)testDBEQ_Zero {
-	[self performDBccTestOpcode:0x57ca status:Flag::Zero d2Outcome:1];
+	[self performDBccTestOpcode:0x57ca status:ConditionCode::Zero d2Outcome:1];
 }
 
 - (void)testDBVC {
@@ -285,7 +287,7 @@
 }
 
 - (void)testDBVC_Overflow {
-	[self performDBccTestOpcode:0x58ca status:Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x58ca status:ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBVS {
@@ -293,7 +295,7 @@
 }
 
 - (void)testDBVS_Overflow {
-	[self performDBccTestOpcode:0x59ca status:Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x59ca status:ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBPL {
@@ -301,7 +303,7 @@
 }
 
 - (void)testDBPL_Negative {
-	[self performDBccTestOpcode:0x5aca status:Flag::Negative d2Outcome:0];
+	[self performDBccTestOpcode:0x5aca status:ConditionCode::Negative d2Outcome:0];
 }
 
 - (void)testDBMI {
@@ -309,11 +311,11 @@
 }
 
 - (void)testDBMI_Negative {
-	[self performDBccTestOpcode:0x5bca status:Flag::Negative d2Outcome:1];
+	[self performDBccTestOpcode:0x5bca status:ConditionCode::Negative d2Outcome:1];
 }
 
 - (void)testDBGE_NegativeOverflow {
-	[self performDBccTestOpcode:0x5cca status:Flag::Negative | Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x5cca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBGE {
@@ -321,15 +323,15 @@
 }
 
 - (void)testDBGE_Negative {
-	[self performDBccTestOpcode:0x5cca status:Flag::Negative d2Outcome:0];
+	[self performDBccTestOpcode:0x5cca status:ConditionCode::Negative d2Outcome:0];
 }
 
 - (void)testDBGE_Overflow {
-	[self performDBccTestOpcode:0x5cca status:Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5cca status:ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBLT_NegativeOverflow {
-	[self performDBccTestOpcode:0x5dca status:Flag::Negative | Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5dca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBLT {
@@ -337,11 +339,11 @@
 }
 
 - (void)testDBLT_Negative {
-	[self performDBccTestOpcode:0x5dca status:Flag::Negative d2Outcome:1];
+	[self performDBccTestOpcode:0x5dca status:ConditionCode::Negative d2Outcome:1];
 }
 
 - (void)testDBLT_Overflow {
-	[self performDBccTestOpcode:0x5dca status:Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x5dca status:ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBGT {
@@ -349,15 +351,15 @@
 }
 
 - (void)testDBGT_ZeroNegativeOverflow {
-	[self performDBccTestOpcode:0x5eca status:Flag::Zero | Flag::Negative | Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5eca status:ConditionCode::Zero | ConditionCode::Negative | ConditionCode::Overflow d2Outcome:0];
 }
 
 - (void)testDBGT_NegativeOverflow {
-	[self performDBccTestOpcode:0x5eca status:Flag::Negative | Flag::Overflow d2Outcome:1];
+	[self performDBccTestOpcode:0x5eca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:1];
 }
 
 - (void)testDBGT_Zero {
-	[self performDBccTestOpcode:0x5eca status:Flag::Zero d2Outcome:0];
+	[self performDBccTestOpcode:0x5eca status:ConditionCode::Zero d2Outcome:0];
 }
 
 - (void)testDBLE {
@@ -365,15 +367,15 @@
 }
 
 - (void)testDBLE_Zero {
-	[self performDBccTestOpcode:0x5fca status:Flag::Zero d2Outcome:1];
+	[self performDBccTestOpcode:0x5fca status:ConditionCode::Zero d2Outcome:1];
 }
 
 - (void)testDBLE_Negative {
-	[self performDBccTestOpcode:0x5fca status:Flag::Negative d2Outcome:1];
+	[self performDBccTestOpcode:0x5fca status:ConditionCode::Negative d2Outcome:1];
 }
 
 - (void)testDBLE_NegativeOverflow {
-	[self performDBccTestOpcode:0x5fca status:Flag::Negative | Flag::Overflow d2Outcome:0];
+	[self performDBccTestOpcode:0x5fca status:ConditionCode::Negative | ConditionCode::Overflow d2Outcome:0];
 }
 
 /* Further DBF tests omitted; they seemed to be duplicative, assuming I'm not suffering a failure of comprehension. */
@@ -385,15 +387,14 @@
 		0x4ed1		// JMP (A1)
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3000);
-	XCTAssertEqual(state.program_counter, 0x3000 + 4);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x3000);
+	XCTAssertEqual(state.registers.program_counter, 0x3000 + 4);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -405,7 +406,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x100c + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x100c + 4);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -414,14 +415,13 @@
 - (void)testJSR_PC {
 	_machine->set_program({
 		0x4eba, 0x000a		// JSR (+a)PC		; JSR to $100c
-	});
-	_machine->set_initial_stack_pointer(0x2000);
+	}, 0x2000);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1ffc);
-	XCTAssertEqual(state.program_counter, 0x100c + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1ffc);
+	XCTAssertEqual(state.registers.program_counter, 0x100c + 4);
 	XCTAssertEqual(*_machine->ram_at(0x1ffc), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x1ffe), 0x1004);
 	XCTAssertEqual(18, _machine->get_cycle_count());
@@ -430,14 +430,13 @@
 - (void)testJSR_XXXl {
 	_machine->set_program({
 		0x4eb9, 0x0000, 0x1008		// JSR ($1008).l
-	});
-	_machine->set_initial_stack_pointer(0x2000);
+	}, 0x2000);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1ffc);
-	XCTAssertEqual(state.program_counter, 0x1008 + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1ffc);
+	XCTAssertEqual(state.registers.program_counter, 0x1008 + 4);
 	XCTAssertEqual(*_machine->ram_at(0x1ffc), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x1ffe), 0x1006);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -458,8 +457,7 @@
 - (void)testRTR {
 	_machine->set_program({
 		0x4e77		// RTR
-	});
-	_machine->set_initial_stack_pointer(0x2000);
+	}, 0x2000);
 	*_machine->ram_at(0x2000) = 0x7fff;
 	*_machine->ram_at(0x2002) = 0;
 	*_machine->ram_at(0x2004) = 0xc;
@@ -467,9 +465,9 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x2006);
-	XCTAssertEqual(state.program_counter, 0x10);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2006);
+	XCTAssertEqual(state.registers.program_counter, 0x10);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -478,16 +476,15 @@
 - (void)testRTS {
 	_machine->set_program({
 		0x4e75		// RTS
-	});
-	_machine->set_initial_stack_pointer(0x2000);
+	}, 0x2000);
 	*_machine->ram_at(0x2000) = 0x0000;
 	*_machine->ram_at(0x2002) = 0x000c;
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x2004);
-	XCTAssertEqual(state.program_counter, 0x000c + 4);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x2004);
+	XCTAssertEqual(state.registers.program_counter, 0x000c + 4);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -497,22 +494,21 @@
 	_machine->set_program({
 		0x4e41		// TRAP #1
 	});
-	auto state = _machine->get_processor_state();
-	state.status = 0x700;
-	state.user_stack_pointer = 0x200;
-	state.supervisor_stack_pointer = 0x206;
+	_machine->set_registers([=](auto &registers) {
+		registers.status = 0x700;
+		registers.user_stack_pointer = 0x200;
+		registers.supervisor_stack_pointer = 0x206;
+	});
 	*_machine->ram_at(0x84) = 0xfffe;
 	*_machine->ram_at(0xfffe) = 0x4e71;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status, 0x2700);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status, 0x2700);
 	XCTAssertEqual(*_machine->ram_at(0x200), 0x700);
 	XCTAssertEqual(*_machine->ram_at(0x202), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x204), 0x1002);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x200);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x200);
 	XCTAssertEqual(34, _machine->get_cycle_count());
 }
 
@@ -521,21 +517,20 @@
 - (void)testTRAPV_taken {
 	_machine->set_program({
 		0x4e76		// TRAPV
-	});
-	_machine->set_initial_stack_pointer(0x206);
+	}, 0x206);
 
-	auto state = _machine->get_processor_state();
-	state.status = 0x702;
-	state.supervisor_stack_pointer = 0x206;
+	_machine->set_registers([=](auto &registers) {
+		registers.status = 0x702;
+		registers.supervisor_stack_pointer = 0x206;
+	});
 	*_machine->ram_at(0x1e) = 0xfffe;
 	*_machine->ram_at(0xfffe) = 0x4e71;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status, 0x2702);
-	XCTAssertEqual(state.stack_pointer(), 0x200);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status, 0x2702);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x200);
 	XCTAssertEqual(*_machine->ram_at(0x202), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x204), 0x1002);
 	XCTAssertEqual(*_machine->ram_at(0x200), 0x702);
@@ -550,7 +545,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.program_counter, 0x1002 + 4);
+	XCTAssertEqual(state.registers.program_counter, 0x1002 + 4);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
diff --git a/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm b/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm
index 27fbd04ac..f23ffbf24 100644
--- a/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000MoveTests.mm	
@@ -32,16 +32,15 @@
 	_machine->set_program({
 		0x4244		// CLR.w D4
 	});
-	auto state = _machine->get_processor_state();
-	state.data[4] = 0x9853abcd;
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[4] = 0x9853abcd;
+		registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[4], 0x98530000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[4], 0x98530000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -49,16 +48,15 @@
 	_machine->set_program({
 		0x4284		// CLR.l D4
 	});
-	auto state = _machine->get_processor_state();
-	state.data[4] = 0x9853abcd;
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[4] = 0x9853abcd;
+		registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[4], 0x0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[4], 0x0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -68,16 +66,15 @@
 	});
 	*_machine->ram_at(0x186a0) = 0x9853;
 	*_machine->ram_at(0x186a2) = 0xabcd;
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x186a0), 0x0);
 	XCTAssertEqual(*_machine->ram_at(0x186a2), 0x0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -87,16 +84,15 @@
 	});
 	*_machine->ram_at(0x186a0) = 0x9853;
 	*_machine->ram_at(0x186a2) = 0xabcd;
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x186a0), 0x0053);
 	XCTAssertEqual(*_machine->ram_at(0x186a2), 0xabcd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -107,16 +103,15 @@
 		0xc342		// EXG D1, D2
 	});
 
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x11111111;
-	state.data[2] = 0x22222222;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x11111111;
+		registers.data[2] = 0x22222222;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x22222222);
-	XCTAssertEqual(state.data[2], 0x11111111);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x22222222);
+	XCTAssertEqual(state.registers.data[2], 0x11111111);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -125,16 +120,15 @@
 		0xc34a		// EXG A1, A2
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x11111111;
-	state.address[2] = 0x22222222;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x11111111;
+		registers.address[2] = 0x22222222;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x22222222);
-	XCTAssertEqual(state.address[2], 0x11111111);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x22222222);
+	XCTAssertEqual(state.registers.address[2], 0x11111111);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -143,16 +137,15 @@
 		0xc389		// EXG A1, D1
 	});
 
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x11111111;
-	state.address[1] = 0x22222222;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x11111111;
+		registers.address[1] = 0x22222222;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x22222222);
-	XCTAssertEqual(state.address[1], 0x11111111);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x22222222);
+	XCTAssertEqual(state.registers.address[1], 0x11111111);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -166,7 +159,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[0], 0xc);
+	XCTAssertEqual(state.registers.address[0], 0xc);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -178,7 +171,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[0], 0xc000d);
+	XCTAssertEqual(state.registers.address[0], 0xc000d);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -187,15 +180,14 @@
 		0x43d2,		// LEA (A2), A1
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xc000d;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xc000d);
-	XCTAssertEqual(state.address[2], 0xc000d);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0xc000d);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -204,15 +196,14 @@
 		0x43ea, 0xffff		// LEA (-1,A2), A1
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xc000d;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xc000c);
-	XCTAssertEqual(state.address[2], 0xc000d);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0xc000c);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -221,17 +212,16 @@
 		0x43f2, 0x7002		// LEA (2,A2,D7.W), A1
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
-	state.data[7] = 0x10000022;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xc000d;
+		registers.data[7] = 0x10000022;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xc0031);
-	XCTAssertEqual(state.address[2], 0xc000d);
-	XCTAssertEqual(state.data[7], 0x10000022);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0xc0031);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
+	XCTAssertEqual(state.registers.data[7], 0x10000022);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -240,17 +230,17 @@
 		0x43f2, 0x7802		// LEA (2,A2,D7.l), A1
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
-	state.data[7] = 0x10000022;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xc000d;
+		registers.data[7] = 0x10000022;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x100c0031);
-	XCTAssertEqual(state.address[2], 0xc000d);
-	XCTAssertEqual(state.data[7], 0x10000022);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x100c0031);
+	XCTAssertEqual(state.registers.address[2], 0xc000d);
+	XCTAssertEqual(state.registers.data[7], 0x10000022);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -259,14 +249,13 @@
 		0x43fa, 0xeff8		// LEA	(-6,PC), A1
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xc000d;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xc000d;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0xFFFFFFFA);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0xFFFFFFFA);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -275,15 +264,14 @@
 		0x43fb, 0x30fe		// LEA (-6,PC,D3), A1
 	});
 
-	auto state = _machine->get_processor_state();
-	state.data[3] = 0x2;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[3] = 0x2;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x1002);
-	XCTAssertEqual(state.data[3], 0x2);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x1002);
+	XCTAssertEqual(state.registers.data[3], 0x2);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -292,17 +280,15 @@
 - (void)testLINKA1_5 {
 	_machine->set_program({
 		0x4e51, 0x0005		// LINK a1, #5
+	}, 0x22222222);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x11111111;
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x11111111;
-	_machine->set_initial_stack_pointer(0x22222222);
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2222221e);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x22222223);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x2222221e);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x22222223);
 	XCTAssertEqual(*_machine->ram_at(0x2222221e), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x22222220), 0x1111);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -311,13 +297,12 @@
 - (void)testLINKA7_5 {
 	_machine->set_program({
 		0x4e57, 0x0005		// LINK a7, #5
-	});
-	_machine->set_initial_stack_pointer(0x22222222);
+	}, 0x22222222);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x22222223);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x22222223);
 	XCTAssertEqual(*_machine->ram_at(0x2222221e), 0x2222);
 	XCTAssertEqual(*_machine->ram_at(0x22222220), 0x221e);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -326,17 +311,15 @@
 - (void)testLINKA1_8000 {
 	_machine->set_program({
 		0x4e51, 0x8000		// LINK a1, #$8000
+	}, 0x22222222);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x11111111;
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x11111111;
-	_machine->set_initial_stack_pointer(0x22222222);
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2222221e);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x2221a21e);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x2222221e);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x2221a21e);
 	XCTAssertEqual(*_machine->ram_at(0x2222221e), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x22222220), 0x1111);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -348,18 +331,17 @@
 	_machine->set_program({
 		0x48e1, 0xc000		// MOVEM.L D0-D1, -(A1)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.data[0] = 0x12345678;
-	state.data[1] = 0x87654321;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+		registers.data[0] = 0x12345678;
+		registers.data[1] = 0x87654321;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2ff8);
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.data[1], 0x87654321);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x2ff8);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.data[1], 0x87654321);
 	XCTAssertEqual(*_machine->ram_at(0x2ff8), 0x1234);
 	XCTAssertEqual(*_machine->ram_at(0x2ffa), 0x5678);
 	XCTAssertEqual(*_machine->ram_at(0x2ffc), 0x8765);
@@ -371,18 +353,17 @@
 	_machine->set_program({
 		0x48e1, 0xc040		// MOVEM.L D0-D1/A1, -(A1)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000;
-	state.data[0] = 0x12345678;
-	state.data[1] = 0x87654321;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000;
+		registers.data[0] = 0x12345678;
+		registers.data[1] = 0x87654321;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x2ff4);
-	XCTAssertEqual(state.data[0], 0x12345678);
-	XCTAssertEqual(state.data[1], 0x87654321);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x2ff4);
+	XCTAssertEqual(state.registers.data[0], 0x12345678);
+	XCTAssertEqual(state.registers.data[1], 0x87654321);
 	XCTAssertEqual(*_machine->ram_at(0x2ff4), 0x1234);
 	XCTAssertEqual(*_machine->ram_at(0x2ff6), 0x5678);
 	XCTAssertEqual(*_machine->ram_at(0x2ff8), 0x8765);
@@ -395,20 +376,18 @@
 - (void)testMOVEMl_fromEverything {
 	_machine->set_program({
 		0x48e4, 0xffff		// MOVEM.L D0-D7/A0-A7, -(A4)
+	}, 0xffffffff);
+	_machine->set_registers([=](auto &registers) {
+		for(int c = 0; c < 8; ++c)
+			registers.data[c] = (c+1) * 0x11111111;
+		for(int c = 0; c < 7; ++c)
+			registers.address[c] = ((c < 4) ? (c + 9) : (c + 8)) * 0x11111111;
+		registers.address[4] = 0x4000;
 	});
-	auto state = _machine->get_processor_state();
-	for(int c = 0; c < 8; ++c)
-		state.data[c] = (c+1) * 0x11111111;
-	for(int c = 0; c < 7; ++c)
-		state.address[c] = ((c < 4) ? (c + 9) : (c + 8)) * 0x11111111;
-	state.address[4] = 0x4000;
-	_machine->set_initial_stack_pointer(0xffffffff);
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[4], 0x3fc0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[4], 0x3fc0);
 
 	const uint32_t expected_values[] = {
 		0xffffffff, 0xeeeeeeee, 0xdddddddd, 0x00004000,
@@ -430,19 +409,18 @@
 	_machine->set_program({
 		0x48a4, 0x0800		// MOVEM.W D4, -(A4)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[4] = 0x4000;
-	state.data[4] = 0x111a1111;
-	state.data[0] = 0xffffffff;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[4] = 0x4000;
+		registers.data[4] = 0x111a1111;
+		registers.data[0] = 0xffffffff;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.address[4], 0x3ffe);
-	XCTAssertEqual(state.data[0], 0xffffffff);
-	XCTAssertEqual(state.data[4], 0x111a1111);
+	XCTAssertEqual(state.registers.address[4], 0x3ffe);
+	XCTAssertEqual(state.registers.data[0], 0xffffffff);
+	XCTAssertEqual(state.registers.data[4], 0x111a1111);
 
 	XCTAssertEqual(*_machine->ram_at(0x3ffe), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x3ffc), 0x0000);
@@ -456,8 +434,9 @@
 	_machine->set_program({
 		0x4cd9, 0x0606		// MOVEM.l (A1)+, D1-D2/A1-A2
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x4000;
+	});
 	*_machine->ram_at(0x4000) = 0x1111;
 	*_machine->ram_at(0x4002) = 0x1111;
 	*_machine->ram_at(0x4004) = 0x2222;
@@ -465,15 +444,14 @@
 	*_machine->ram_at(0x400c) = 0x3333;
 	*_machine->ram_at(0x400e) = 0x3333;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.data[1], 0x11111111);
-	XCTAssertEqual(state.data[2], 0x22222222);
-	XCTAssertEqual(state.address[1], 0x4010);
-	XCTAssertEqual(state.address[2], 0x33333333);
+	XCTAssertEqual(state.registers.data[1], 0x11111111);
+	XCTAssertEqual(state.registers.data[2], 0x22222222);
+	XCTAssertEqual(state.registers.address[1], 0x4010);
+	XCTAssertEqual(state.registers.address[2], 0x33333333);
 
 	XCTAssertEqual(44, _machine->get_cycle_count());
 }
@@ -482,17 +460,17 @@
 	_machine->set_program({
 		0x4c99, 0x0002		// MOVEM.w (A1)+, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x4000;
+	});
 	*_machine->ram_at(0x4000) = 0x8000;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.data[1], 0xffff8000);
-	XCTAssertEqual(state.address[1], 0x4002);
+	XCTAssertEqual(state.registers.data[1], 0xffff8000);
+	XCTAssertEqual(state.registers.address[1], 0x4002);
 
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
@@ -501,21 +479,21 @@
 	_machine->set_program({
 		0x4c91, 0x0206		// MOVEM.w (A1), A1/D1-D2
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
-	state.data[2] = 0xffffffff;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x4000;
+		registers.data[2] = 0xffffffff;
+	});
 	*_machine->ram_at(0x4000) = 0x8000;
 	*_machine->ram_at(0x4002) = 0x2222;
 	*_machine->ram_at(0x4004) = 0x3333;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 
-	XCTAssertEqual(state.data[1], 0xffff8000);
-	XCTAssertEqual(state.data[2], 0x00002222);
-	XCTAssertEqual(state.address[1], 0x3333);
+	XCTAssertEqual(state.registers.data[1], 0xffff8000);
+	XCTAssertEqual(state.registers.data[2], 0x00002222);
+	XCTAssertEqual(state.registers.address[1], 0x3333);
 
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
@@ -524,20 +502,19 @@
 	_machine->set_program({
 		0x4891, 0x0206		// MOVEM.w A1/D1-D2, (A1)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x4000;
-	state.data[1] = 0x11111111;
-	state.data[2] = 0x22222222;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x4000;
+		registers.data[1] = 0x11111111;
+		registers.data[2] = 0x22222222;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 
 	XCTAssertEqual(*_machine->ram_at(0x4000), 0x1111);
 	XCTAssertEqual(*_machine->ram_at(0x4002), 0x2222);
 	XCTAssertEqual(*_machine->ram_at(0x4004), 0x4000);
-	XCTAssertEqual(state.address[1], 0x4000);
+	XCTAssertEqual(state.registers.address[1], 0x4000);
 
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
@@ -548,16 +525,16 @@
 	_machine->set_program({
 		0x1401		// MOVE.b D1, D2
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12345678;
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x12345678;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.data[2], 0x00000078);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.data[2], 0x00000078);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -569,8 +546,8 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[2], 0x8090fea1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[2], 0x8090fea1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -578,16 +555,16 @@
 	_machine->set_program({
 		0x34bc, 0x0000		// MOVE #$0, (A2)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0x3000;
+	});
 	*_machine->ram_at(0x3000) = 0x1234;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
@@ -596,18 +573,18 @@
 	_machine->set_program({
 		0x24da		// MOVE.l (A2)+, (A2)+
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
-	state.status = Flag::Negative;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0x3000;
+		registers.status = ConditionCode::Negative;
+	});
 	*_machine->ram_at(0x3000) = 0xaaaa;
 	*_machine->ram_at(0x3002) = 0xbbbb;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3008);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0x3008);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaaaa);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xbbbb);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0xaaaa);
@@ -619,18 +596,18 @@
 	_machine->set_program({
 		0x251a		// MOVE.l (A2)+, -(A2)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3000;
-	state.status = Flag::Negative;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0x3000;
+		registers.status = ConditionCode::Negative;
+	});
 	*_machine->ram_at(0x3000) = 0xaaaa;
 	*_machine->ram_at(0x3002) = 0xbbbb;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0x3000);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaaaa);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xbbbb);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0);
@@ -642,20 +619,20 @@
 	_machine->set_program({
 		0x25a2, 0x1004		// MOVE.L -(A2), 4(A2,D1)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0x3004;
-	state.data[1] = 0;
-	state.status = Flag::Negative;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0x3004;
+		registers.data[1] = 0;
+		registers.status = ConditionCode::Negative;
+	});
 	*_machine->ram_at(0x3000) = 0xaaaa;
 	*_machine->ram_at(0x3002) = 0xbbbb;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x3000);
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0x3000);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaaaa);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xbbbb);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0xaaaa);
@@ -667,15 +644,15 @@
 	_machine->set_program({
 		0x33c1, 0x0000, 0x3000		// MOVE.W D1, ($3000).L
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x5678;
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x5678;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x5678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x5678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x5678);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -690,7 +667,7 @@
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);	/* !! 8 !! */
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);	/* !! 8 !! */
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xeeee);
 	XCTAssertEqual(*_machine->ram_at(0x3006), 0xeeee);
 	XCTAssertEqual(36, _machine->get_cycle_count());
@@ -702,15 +679,15 @@
 	_machine->set_program({
 		0x244a		// MOVEA.l A2, A2
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xffffffff;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -718,17 +695,16 @@
 	_machine->set_program({
 		0x3442		// MOVEA.w D2, A2
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
-	state.data[2] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xffffffff;
+		registers.data[2] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0x00005678);
-	XCTAssertEqual(state.data[2], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0x00005678);
+	XCTAssertEqual(state.registers.data[2], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -736,17 +712,16 @@
 	_machine->set_program({
 		0x3442		// MOVEA.w D2, A2
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
-	state.data[2] = 0x12348756;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xffffffff;
+		registers.data[2] = 0x12348756;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 0xffff8756);
-	XCTAssertEqual(state.data[2], 0x12348756);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 0xffff8756);
+	XCTAssertEqual(state.registers.data[2], 0x12348756);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -754,15 +729,14 @@
 	_machine->set_program({
 		0x247c, 0x0000, 0x0001		// MOVEA.L #$1, A2
 	});
-	auto state = _machine->get_processor_state();
-	state.address[2] = 0xffffffff;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[2] = 0xffffffff;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[2], 1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[2], 1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
@@ -772,18 +746,17 @@
 	_machine->set_program({
 		0x030e, 0x0004		// MOVEP.w 4(A6), D1
 	});
-	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[6] = 0x3000;
+	});
 	*_machine->ram_at(0x3004) = 0x1200;
 	*_machine->ram_at(0x3006) = 0x3400;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
-	XCTAssertEqual(state.data[1], 0x1234);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[6], 0x3000);
+	XCTAssertEqual(state.registers.data[1], 0x1234);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -791,20 +764,20 @@
 	_machine->set_program({
 		0x034e, 0x0002		// MOVEP.l 2(A6), D1
 	});
-	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[6] = 0x3000;
+	});
 	*_machine->ram_at(0x3002) = 0x1200;
 	*_machine->ram_at(0x3004) = 0x3400;
 	*_machine->ram_at(0x3006) = 0x5600;
 	*_machine->ram_at(0x3008) = 0x7800;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
-	XCTAssertEqual(state.data[1], 0x12345678);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[6], 0x3000);
+	XCTAssertEqual(state.registers.data[1], 0x12345678);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -812,19 +785,18 @@
 	_machine->set_program({
 		0x038e, 0x0002		// MOVEP.w D1, 2(A6)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
-	state.data[1] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[6] = 0x3000;
+		registers.data[1] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[6], 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x5600);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0x7800);
 
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -832,22 +804,22 @@
 	_machine->set_program({
 		0x03ce, 0x0002		// MOVEP.l D1, 2(A6)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
-	state.data[1] = 0x12345678;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[6] = 0x3000;
+		registers.data[1] = 0x12345678;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x3000);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[6], 0x3000);
 
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x1200);
 	XCTAssertEqual(*_machine->ram_at(0x3004), 0x3400);
 	XCTAssertEqual(*_machine->ram_at(0x3006), 0x5600);
 	XCTAssertEqual(*_machine->ram_at(0x3008), 0x7800);
 
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -857,15 +829,14 @@
 	_machine->set_program({
 		0x7201		// MOVEQ #1, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xffffffff;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xffffffff;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x1);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x1);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -873,16 +844,15 @@
 	_machine->set_program({
 		0x72ff		// MOVEQ #-1, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+	});
 
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffffffff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xffffffff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -890,16 +860,16 @@
 	_machine->set_program({
 		0x7280		// MOVEQ #$80, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[1] = 0x12345678;
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+		registers.data[1] = 0x12345678;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffffff80);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xffffff80);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -907,16 +877,15 @@
 	_machine->set_program({
 		0x7200		// MOVEQ #00, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[1] = 0x12345678;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+		registers.data[1] = 0x12345678;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Zero);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -926,15 +895,14 @@
 	_machine->set_program({
 		0x40c1		// MOVE SR, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.status = 0x271f;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.status = 0x271f;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x271f);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x271f);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -944,14 +912,14 @@
 	_machine->set_program({
 		0x44fc, 0x001f		// MOVE #$1f, CCR
 	});
-	auto state = _machine->get_processor_state();
-	state.status = 0;	// i.e. not even supervisor.
+	_machine->set_registers([=](auto &registers) {
+		registers.status = 0;	// i.e. not supervisor.
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0x1f);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0x1f);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -961,16 +929,15 @@
 	_machine->set_program({
 		0x46fc, 0x0700		// MOVE #$700, SR
 	});
-	auto state = _machine->get_processor_state();
-	state.supervisor_stack_pointer = 0x3000;
-	state.user_stack_pointer = 0;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.supervisor_stack_pointer = 0x3000;
+		registers.user_stack_pointer = 0;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.stack_pointer(), 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -980,14 +947,14 @@
 	_machine->set_program({
 		0x4e69		// MOVE USP, A1
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x12348756;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x12348756;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0);
 }
 
 // MARK: PEA
@@ -995,17 +962,15 @@
 - (void)testPEA_A1 {
 	_machine->set_program({
 		0x4851		// PEA (A1)
+	}, 0x1996);
+	_machine->set_registers([=](auto &registers) {
+		registers.address[1] = 0x3000ffff;
 	});
-	auto state = _machine->get_processor_state();
-	state.address[1] = 0x3000ffff;
-	_machine->set_initial_stack_pointer(0x1996);
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[1], 0x3000ffff);
-	XCTAssertEqual(state.stack_pointer(), 0x1992);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.address[1], 0x3000ffff);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1992);
 	XCTAssertEqual(*_machine->ram_at(0x1992), 0x3000);
 	XCTAssertEqual(*_machine->ram_at(0x1994), 0xffff);
 	XCTAssertEqual(12, _machine->get_cycle_count());
@@ -1014,13 +979,12 @@
 - (void)testPEA_A7 {
 	_machine->set_program({
 		0x4857		// PEA (A7)
-	});
-	_machine->set_initial_stack_pointer(0x1012);
+	}, 0x1012);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x100e);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x100e);
 	XCTAssertEqual(*_machine->ram_at(0x1010), 0x1012);
 	XCTAssertEqual(*_machine->ram_at(0x1008), 0x0000);
 	XCTAssertEqual(12, _machine->get_cycle_count());
@@ -1029,13 +993,12 @@
 - (void)testPEA_4A7 {
 	_machine->set_program({
 		0x486f, 0x0004		// PEA 4(A7)
-	});
-	_machine->set_initial_stack_pointer(0x1012);
+	}, 0x1012);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x100e);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x100e);
 	XCTAssertEqual(*_machine->ram_at(0x1010), 0x1016);
 	XCTAssertEqual(*_machine->ram_at(0x1008), 0x0000);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -1044,13 +1007,12 @@
 - (void)testPEA_XXXw {
 	_machine->set_program({
 		0x4878, 0x3000		// PEA ($3000).w
-	});
-	_machine->set_initial_stack_pointer(0x1996);
+	}, 0x1996);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1992);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1992);
 	XCTAssertEqual(*_machine->ram_at(0x1992), 0x0000);
 	XCTAssertEqual(*_machine->ram_at(0x1994), 0x3000);
 	XCTAssertEqual(16, _machine->get_cycle_count());
@@ -1059,13 +1021,12 @@
 - (void)testPEA_XXXl {
 	_machine->set_program({
 		0x4879, 0x1234, 0x5678		// PEA ($12345678)
-	});
-	_machine->set_initial_stack_pointer(0x1996);
+	}, 0x1996);
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.stack_pointer(), 0x1992);
+	XCTAssertEqual(state.registers.stack_pointer(), 0x1992);
 	XCTAssertEqual(*_machine->ram_at(0x1992), 0x1234);
 	XCTAssertEqual(*_machine->ram_at(0x1994), 0x5678);
 	XCTAssertEqual(20, _machine->get_cycle_count());
@@ -1077,82 +1038,79 @@
 	_machine->set_program({
 		0x51c0		// SF D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.status = Flag::Extend;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0x12345678;
+		registers.status = ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x12345600);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x12345600);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testSTDn {
 	_machine->set_program({
 		0x50c0		// ST D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.status = Flag::Extend;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0x12345678;
+		registers.status = ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x123456ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x123456ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testSLSDn {
 	_machine->set_program({
 		0x53c0		// SLS D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0x12345678;
-	state.status = Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0x12345678;
+		registers.status = ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x123456ff);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x123456ff);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 - (void)testSGTAnXTrue {
 	_machine->set_program({
 		0x5ee8, 0x0002		// SGT 2(a0)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[0] = 0x3000;
+		registers.status = ConditionCode::Extend;
+	});
 	*_machine->ram_at(0x3002) = 0x8800;
-	state.status = Flag::Extend;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0xff00);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 }
 
 - (void)testSGTAnXFalse {
 	_machine->set_program({
 		0x5ee8, 0x0002		// SGT 2(a0)
 	});
-	auto state = _machine->get_processor_state();
-	state.address[0] = 0x3000;
+	_machine->set_registers([=](auto &registers) {
+		registers.address[0] = 0x3000;
+		registers.status = ConditionCode::AllConditions;
+	});
 	*_machine->ram_at(0x3002) = 0x8800;
-	state.status = Flag::ConditionCodes;
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0000);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::ConditionCodes);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::AllConditions);
 }
 
 
@@ -1162,15 +1120,14 @@
 	_machine->set_program({
 		0x4841		// SWAP D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0x12348756;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0x12348756;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x87561234);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x87561234);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 }
 
 // MARK: TST
@@ -1179,16 +1136,16 @@
 	_machine->set_program({
 		0x4a44		// TST.w D4
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[4] = 0xfff1;
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+		registers.data[4] = 0xfff1;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend);
-	XCTAssertEqual(state.data[4], 0xfff1);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[4], 0xfff1);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1196,16 +1153,16 @@
 	_machine->set_program({
 		0x4a84		// TST.l D4
 	});
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend | Flag::Carry | Flag::Overflow;
-	state.data[4] = 0;
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Overflow;
+		registers.data[4] = 0;
+	});
 
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero | Flag::Extend);
-	XCTAssertEqual(state.data[4], 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero | ConditionCode::Extend);
+	XCTAssertEqual(state.registers.data[4], 0);
 	XCTAssertEqual(4, _machine->get_cycle_count());
 }
 
@@ -1218,32 +1175,31 @@
 		0x4e5e		// UNLNK A6
 	});
 
-	auto state = _machine->get_processor_state();
-	state.address[6] = 0x3000;
-	*_machine->ram_at(0x3000) = 0x0000;
-	*_machine->ram_at(0x3002) = 0x4000;
-
-	_machine->set_processor_state(state);
-	_machine->run_for_instructions(1);
-
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.address[6], 0x4000);
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x3004);
-	XCTAssertEqual(12, _machine->get_cycle_count());
-}
-
-- (void)testUNLINK_A7 {
-	_machine->set_program({
-		0x4e5f		// UNLNK A7
+	_machine->set_registers([=](auto &registers) {
+		registers.address[6] = 0x3000;
 	});
-	_machine->set_initial_stack_pointer(0x3000);
 	*_machine->ram_at(0x3000) = 0x0000;
 	*_machine->ram_at(0x3002) = 0x4000;
 
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.supervisor_stack_pointer, 0x4000);
+	XCTAssertEqual(state.registers.address[6], 0x4000);
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x3004);
+	XCTAssertEqual(12, _machine->get_cycle_count());
+}
+
+- (void)testUNLINK_A7 {
+	_machine->set_program({
+		0x4e5f		// UNLNK A7
+	}, 0x3000);
+	*_machine->ram_at(0x3000) = 0x0000;
+	*_machine->ram_at(0x3002) = 0x4000;
+
+	_machine->run_for_instructions(1);
+
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.supervisor_stack_pointer, 0x4000);
 	XCTAssertEqual(12, _machine->get_cycle_count());
 }
 
diff --git a/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm b/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm
index 24b85da5b..587c41e80 100644
--- a/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000RollShiftTests.mm	
@@ -33,17 +33,16 @@
 	_machine->set_program({
 		0xe521		// ASL.B D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 2;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd59c);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Overflow | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd59c);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Overflow | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -51,17 +50,16 @@
 	_machine->set_program({
 		0xe521		// ASL.B D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 105;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 105;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 105);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 105);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -69,17 +67,16 @@
 	_machine->set_program({
 		0xe561		// ASL.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -87,17 +84,16 @@
 	_machine->set_program({
 		0xe561		// ASL.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0xb;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3d3800);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Overflow | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3d3800);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -105,17 +101,16 @@
 	_machine->set_program({
 		0xe5a1		// ASL.l D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x20;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Overflow | Flag::Carry | Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Overflow | ConditionCode::Carry | ConditionCode::Zero);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -123,16 +118,15 @@
 	_machine->set_program({
 		0xe181		// ASL.l #8, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x20;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x3dd56700);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x3dd56700);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -146,7 +140,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1998);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -162,7 +156,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x8af0);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0782);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Overflow | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Overflow | ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -172,17 +166,16 @@
 	_machine->set_program({
 		0xe421		// ASR.B D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 2;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd519);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd519);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -190,17 +183,16 @@
 	_machine->set_program({
 		0xe421		// ASR.B D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 105;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 105;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 105);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 105);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -208,17 +200,16 @@
 	_machine->set_program({
 		0xe461		// ASR.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -226,17 +217,16 @@
 	_machine->set_program({
 		0xe461		// ASR.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0xb;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dfffa);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dfffa);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -244,17 +234,16 @@
 	_machine->set_program({
 		0xe4a1		// ASR.l D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x20;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffffffff);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xffffffff);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -262,16 +251,15 @@
 	_machine->set_program({
 		0xe081		// ASR.l #8, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x20;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xffce3dd5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xffce3dd5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -285,7 +273,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xc666);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -301,7 +289,7 @@
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xc2bc);
 	XCTAssertEqual(*_machine->ram_at(0x3002), 0x0782);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -311,17 +299,16 @@
 	_machine->set_program({
 		0xe529		// LSL.b D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 2;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd59c);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd59c);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -329,17 +316,16 @@
 	_machine->set_program({
 		0xe529		// LSL.b D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x69;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x69;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 0x69);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 0x69);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -347,17 +333,16 @@
 	_machine->set_program({
 		0xe569		// LSL.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -365,17 +350,16 @@
 	_machine->set_program({
 		0xe569		// LSL.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0xb;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3d3800);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3d3800);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -383,17 +367,16 @@
 	_machine->set_program({
 		0xe5a9		// LSL.l D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x20;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -401,15 +384,14 @@
 	_machine->set_program({
 		0xe189		// LSL.l #8, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0x3dd56700);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0x3dd56700);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -423,7 +405,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x1998);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -433,17 +415,16 @@
 	_machine->set_program({
 		0xe429		// LSR.b D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 2;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 2;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd519);
-	XCTAssertEqual(state.data[2], 2);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd519);
+	XCTAssertEqual(state.registers.data[2], 2);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -451,17 +432,16 @@
 	_machine->set_program({
 		0xe429		// LSR.b D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x69;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x69;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd500);
-	XCTAssertEqual(state.data[2], 0x69);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd500);
+	XCTAssertEqual(state.registers.data[2], 0x69);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 	XCTAssertEqual(88, _machine->get_cycle_count());
 }
 
@@ -469,17 +449,16 @@
 	_machine->set_program({
 		0xe469		// LSR.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd567);
-	XCTAssertEqual(state.data[2], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[2], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -487,17 +466,16 @@
 	_machine->set_program({
 		0xe469		// LSR.w D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0xb;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0xb;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3d001a);
-	XCTAssertEqual(state.data[2], 0xb);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3d001a);
+	XCTAssertEqual(state.registers.data[2], 0xb);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(28, _machine->get_cycle_count());
 }
 
@@ -505,17 +483,16 @@
 	_machine->set_program({
 		0xe4a9		// LSR.l D2, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-	state.data[2] = 0x20;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+		registers.data[2] = 0x20;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.data[2], 0x20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry | Flag::Zero);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.data[2], 0x20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry | ConditionCode::Zero);
 	XCTAssertEqual(72, _machine->get_cycle_count());
 }
 
@@ -523,15 +500,14 @@
 	_machine->set_program({
 		0xe089		// LSR.L #8, D1
 	});
-	auto state = _machine->get_processor_state();
-	state.data[1] = 0xce3dd567;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[1] = 0xce3dd567;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], 0xce3dd5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], 0xce3dd5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -545,7 +521,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x4666);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -555,15 +531,14 @@
 	_machine->set_program({
 		0xe118		// ROL.B #8, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -571,15 +546,14 @@
 	_machine->set_program({
 		0xe318		// ROL.B #1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd5ce);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3dd5ce);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -587,16 +561,15 @@
 	_machine->set_program({
 		0xe518		// ROL.B #2, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.status = ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd59d);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3dd59d);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(10, _machine->get_cycle_count());
 }
 
@@ -604,16 +577,15 @@
 	_machine->set_program({
 		0xef18		// ROL.B #7, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.status = ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd5b3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3dd5b3);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -621,16 +593,15 @@
 	_machine->set_program({
 		0xe158		// ROL.w #7, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.status = ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d67d5);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3d67d5);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -638,16 +609,15 @@
 	_machine->set_program({
 		0xe798		// ROL.l #3, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.status = Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.status = ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x71eeab3e);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x71eeab3e);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(14, _machine->get_cycle_count());
 }
 
@@ -655,39 +625,38 @@
 	_machine->set_program({
 		0xe378		// ROL.l D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = d1;
-	state.status = Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.data[1] = d1;
+		registers.status = ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 }
 
 - (void)testROLw_D1D0_20 {
 	[self performROLw_D1D0d1:20];
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d567d);
-	XCTAssertEqual(state.data[1], 20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3d567d);
+	XCTAssertEqual(state.registers.data[1], 20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(46, _machine->get_cycle_count());
 }
 
 - (void)testROLw_D1D0_36 {
 	[self performROLw_D1D0d1:36];
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d567d);
-	XCTAssertEqual(state.data[1], 36);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	XCTAssertEqual(state.registers.data[0], 0xce3d567d);
+	XCTAssertEqual(state.registers.data[1], 36);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(78, _machine->get_cycle_count());
 }
 
 - (void)testROLw_D1D0_0 {
 	[self performROLw_D1D0d1:0];
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.data[1], 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[1], 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(6, _machine->get_cycle_count());
 }
 
@@ -695,18 +664,17 @@
 	_machine->set_program({
 		0xe3b8		// ROL.l D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 200;
-	state.status = Flag::ConditionCodes;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.data[1] = 200;
+		registers.status = ConditionCode::AllConditions;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x3dd567ce);
-	XCTAssertEqual(state.data[1], 200);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x3dd567ce);
+	XCTAssertEqual(state.registers.data[1], 200);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend);
 	XCTAssertEqual(24, _machine->get_cycle_count());
 }
 
@@ -726,7 +694,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaacf);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 }
 
 - (void)testROLm_0 {
@@ -734,7 +702,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Zero);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Zero);
 }
 
 // MARK: ROR
@@ -744,10 +712,9 @@
 	_machine->set_program({
 		uint16_t(0xe018 | (immediate << 9))		// ROR.b #, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd599;
+	});
 	_machine->run_for_instructions(1);
 }
 
@@ -755,8 +722,8 @@
 	[self performRORbIMM:8];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd599);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd599);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(22, _machine->get_cycle_count());
 }
 
@@ -764,8 +731,8 @@
 	[self performRORbIMM:1];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd5cc);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd5cc);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(8, _machine->get_cycle_count());
 }
 
@@ -773,8 +740,8 @@
 	[self performRORbIMM:4];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd599);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd599);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(14, _machine->get_cycle_count());
 }
 
@@ -782,8 +749,8 @@
 	[self performRORbIMM:7];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd533);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd533);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(20, _machine->get_cycle_count());
 }
 
@@ -791,15 +758,14 @@
 	_machine->set_program({
 		0xec58		// ROR.w #6, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd599;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d6756);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3d6756);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -807,15 +773,14 @@
 	_machine->set_program({
 		0xea98		// ROR.l #5, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd599;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce71eeac);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce71eeac);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(18, _machine->get_cycle_count());
 }
 
@@ -823,17 +788,16 @@
 	_machine->set_program({
 		0xe238		// ROR.b D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
-	state.data[1] = 20;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd599;
+		registers.data[1] = 20;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd599);
-	XCTAssertEqual(state.data[1], 20);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3dd599);
+	XCTAssertEqual(state.registers.data[1], 20);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(46, _machine->get_cycle_count());
 }
 
@@ -841,17 +805,16 @@
 	_machine->set_program({
 		0xe2b8		// ROR.l D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd599;
-	state.data[1] = 26;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd599;
+		registers.data[1] = 26;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x8f756673);
-	XCTAssertEqual(state.data[1], 26);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Negative);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x8f756673);
+	XCTAssertEqual(state.registers.data[1], 26);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Negative);
 	XCTAssertEqual(60, _machine->get_cycle_count());
 }
 
@@ -871,7 +834,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xeab3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry);
 }
 
 - (void)testRORm_d560 {
@@ -879,7 +842,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0x6ab0);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 // MARK: ROXL
@@ -888,74 +851,72 @@
 	_machine->set_program({
 		0xe330		// ROXL.b D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 9;
-	state.status |= ccr;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.data[1] = 9;
+		registers.status |= ccr;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(24, _machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.data[1], 9);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[1], 9);
 }
 
 - (void)testROXLb_extend {
-	[self performROXLb_Dnccr:Flag::ConditionCodes];
+	[self performROXLb_Dnccr:ConditionCode::AllConditions];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testROXLb {
 	[self performROXLb_Dnccr:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)performROXLw_Dnd1:(uint32_t)d1 ccr:(uint16_t)ccr {
 	_machine->set_program({
 		0xe370		// ROXL.w D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = d1;
-	state.status |= ccr;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.data[1] = d1;
+		registers.status |= ccr;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testROXLw_17 {
-	[self performROXLw_Dnd1:17 ccr:Flag::Carry];
+	[self performROXLw_Dnd1:17 ccr:ConditionCode::Carry];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(40, _machine->get_cycle_count());
 }
 
 - (void)testROXLw_5 {
-	[self performROXLw_Dnd1:5 ccr:Flag::Extend];
+	[self performROXLw_Dnd1:5 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dacfd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dacfd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
 - (void)testROXLw_22 {
-	[self performROXLw_Dnd1:22 ccr:Flag::Extend];
+	[self performROXLw_Dnd1:22 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dacfd);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dacfd);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(50, _machine->get_cycle_count());
 }
 
@@ -963,17 +924,16 @@
 	_machine->set_program({
 		0xe3b0		// ROXL.l D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 33;
-	state.status |= Flag::Extend;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.data[1] = 33;
+		registers.status |= ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative | Flag::Carry | Flag::Extend);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative | ConditionCode::Carry | ConditionCode::Extend);
 	XCTAssertEqual(74, _machine->get_cycle_count());
 }
 
@@ -981,16 +941,15 @@
 	_machine->set_program({
 		0xe950		// ROXL.w #4, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3d3600;
-	state.status |= Flag::Extend;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3d3600;
+		registers.status |= ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d6009);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Extend | Flag::Carry);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0xce3d6009);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Extend | ConditionCode::Carry);
 	XCTAssertEqual(14, _machine->get_cycle_count());
 }
 
@@ -1004,7 +963,7 @@
 
 	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xaace);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -1014,74 +973,72 @@
 	_machine->set_program({
 		0xe230		// ROXR.b D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = 9;
-	state.status |= ccr;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.data[1] = 9;
+		registers.status |= ccr;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(24, _machine->get_cycle_count());
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.data[1], 9);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.data[1], 9);
 }
 
 - (void)testROXRb_extend {
-	[self performROXRb_Dnccr:Flag::ConditionCodes];
+	[self performROXRb_Dnccr:ConditionCode::AllConditions];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend);
 }
 
 - (void)testROXRb {
 	[self performROXRb_Dnccr:0];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 }
 
 - (void)performROXRw_Dnd1:(uint32_t)d1 ccr:(uint16_t)ccr {
 	_machine->set_program({
 		0xe270		// ROXR.w D1, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3dd567;
-	state.data[1] = d1;
-	state.status |= ccr;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3dd567;
+		registers.data[1] = d1;
+		registers.status |= ccr;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[1], d1);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[1], d1);
 }
 
 - (void)testROXRw_17 {
-	[self performROXRw_Dnd1:17 ccr:Flag::Carry];
+	[self performROXRw_Dnd1:17 ccr:ConditionCode::Carry];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3dd567);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Negative);
+	XCTAssertEqual(state.registers.data[0], 0xce3dd567);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Negative);
 	XCTAssertEqual(40, _machine->get_cycle_count());
 }
 
 - (void)testROXRw_5 {
-	[self performROXRw_Dnd1:5 ccr:Flag::Extend];
+	[self performROXRw_Dnd1:5 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d7eab);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0xce3d7eab);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
 - (void)testROXRw_22 {
-	[self performROXRw_Dnd1:22 ccr:Flag::Extend];
+	[self performROXRw_Dnd1:22 ccr:ConditionCode::Extend];
 
 	const auto state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0xce3d7eab);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	XCTAssertEqual(state.registers.data[0], 0xce3d7eab);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(50, _machine->get_cycle_count());
 }
 
@@ -1089,16 +1046,15 @@
 	_machine->set_program({
 		0xe890		// ROXR.L #4, D0
 	});
-	auto state = _machine->get_processor_state();
-	state.data[0] = 0xce3d3600;
-	state.status |= Flag::Extend;
-
-	_machine->set_processor_state(state);
+	_machine->set_registers([=](auto &registers) {
+		registers.data[0] = 0xce3d3600;
+		registers.status |= ConditionCode::Extend;
+	});
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
-	XCTAssertEqual(state.data[0], 0x1ce3d360);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, 0);
+	const auto state = _machine->get_processor_state();
+	XCTAssertEqual(state.registers.data[0], 0x1ce3d360);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, 0);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
@@ -1106,16 +1062,15 @@
 	_machine->set_program({
 		0xe4f8, 0x3000		// ROXR.W ($3000).W
 	});
+	_machine->set_registers([=](auto &registers) {
+		registers.status |= ConditionCode::Extend;
+	});
 	*_machine->ram_at(0x3000) = 0xd567;
-	auto state = _machine->get_processor_state();
-	state.status |= Flag::Extend;
-
-	_machine->set_processor_state(state);
 	_machine->run_for_instructions(1);
 
-	state = _machine->get_processor_state();
+	const auto state = _machine->get_processor_state();
 	XCTAssertEqual(*_machine->ram_at(0x3000), 0xeab3);
-	XCTAssertEqual(state.status & Flag::ConditionCodes, Flag::Carry | Flag::Extend | Flag::Negative);
+	XCTAssertEqual(state.registers.status & ConditionCode::AllConditions, ConditionCode::Carry | ConditionCode::Extend | ConditionCode::Negative);
 	XCTAssertEqual(16, _machine->get_cycle_count());
 }
 
diff --git a/OSBindings/Mac/Clock SignalTests/68000Tests.mm b/OSBindings/Mac/Clock SignalTests/68000Tests.mm
index dc524b328..8cebc0385 100644
--- a/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/68000Tests.mm	
@@ -12,94 +12,25 @@
 
 #include "TestRunner68000.hpp"
 
-class CPU::MC68000::ProcessorStorageTests {
-	public:
-		ProcessorStorageTests(const CPU::MC68000::ProcessorStorage &storage, const char *coverage_file_name) {
-			false_valids_ = [NSMutableSet set];
-			false_invalids_ = [NSMutableSet set];
-
-			FILE *source = fopen(coverage_file_name, "rb");
-
-			// The file format here is [2 bytes opcode][2 ASCII characters:VA for valid, IN for invalid]...
-			// The file terminates with four additional bytes that begin with two zero bytes.
-			//
-			// The version of the file I grabbed seems to cover all opcodes, making their enumeration
-			// arguably redundant; the code below nevertheless uses the codes from the file.
-			//
-			// Similarly, I'm testing for exactly the strings VA or IN to ensure no further
-			// types creep into any updated version of the table that I then deal with incorrectly.
-			uint16_t last_observed = 0;
-			while(true) {
-				// Fetch opcode number.
-				uint16_t next_opcode = fgetc(source) << 8;
-				next_opcode |= fgetc(source);
-				if(next_opcode < last_observed) break;
-				last_observed = next_opcode;
-
-				// Determine whether it's meant to be valid.
-				char type[3];
-				type[0] = fgetc(source);
-				type[1] = fgetc(source);
-				type[2] = '\0';
-
-				// TEMPORARY: factor out A- and F-line exceptions.
-				if((next_opcode&0xf000) == 0xa000) continue;
-				if((next_opcode&0xf000) == 0xf000) continue;
-
-				if(!strcmp(type, "VA")) {
-					// Test for validity.
-					if(storage.instructions[next_opcode].micro_operations == std::numeric_limits<uint32_t>::max()) {
-						[false_invalids_ addObject:@(next_opcode)];
-					}
-					continue;
-				}
-
-				if(!strcmp(type, "IN")) {
-					// Test for invalidity.
-					if(storage.instructions[next_opcode].micro_operations != std::numeric_limits<uint32_t>::max()) {
-						[false_valids_ addObject:@(next_opcode)];
-					}
-					continue;
-				}
-
-				assert(false);
-			}
-
-			fclose(source);
-		}
-
-		NSSet<NSNumber *> *false_valids() const {
-			return false_valids_;
-		}
-
-		NSSet<NSNumber *> *false_invalids() const {
-			return false_invalids_;
-		}
-
-	private:
-		NSMutableSet<NSNumber *> *false_invalids_;
-		NSMutableSet<NSNumber *> *false_valids_;
-};
-
-@interface NSSet (CSHexDump)
-
-- (NSString *)hexDump;
-
-@end
-
-@implementation NSSet (CSHexDump)
-
-- (NSString *)hexDump {
-	NSMutableArray<NSString *> *components = [NSMutableArray array];
-
-	for(NSNumber *number in [[self allObjects] sortedArrayUsingSelector:@selector(compare:)]) {
-		[components addObject:[NSString stringWithFormat:@"%04x", number.intValue]];
-	}
-
-	return [components componentsJoinedByString:@" "];
-}
-
-@end
+//@interface NSSet (CSHexDump)
+//
+//- (NSString *)hexDump;
+//
+//@end
+//
+//@implementation NSSet (CSHexDump)
+//
+//- (NSString *)hexDump {
+//	NSMutableArray<NSString *> *components = [NSMutableArray array];
+//
+//	for(NSNumber *number in [[self allObjects] sortedArrayUsingSelector:@selector(compare:)]) {
+//		[components addObject:[NSString stringWithFormat:@"%04x", number.intValue]];
+//	}
+//
+//	return [components componentsJoinedByString:@" "];
+//}
+//
+//@end
 
 
 @interface M68000Tests : XCTestCase
@@ -123,39 +54,38 @@ class CPU::MC68000::ProcessorStorageTests {
 		_machine->set_program({
 			0xc100		// ABCD D0, D0
 		});
-
-		auto state = _machine->get_processor_state();
 		const uint8_t bcd_d = ((d / 10) * 16) + (d % 10);
-		state.data[0] = bcd_d;
-		_machine->set_processor_state(state);
-
+		_machine->set_registers([=](auto &registers){
+			registers.data[0] = bcd_d;
+		});
 		_machine->run_for_instructions(1);
 
-		state = _machine->get_processor_state();
+		const auto state = _machine->get_processor_state();
 		const uint8_t double_d = (d * 2) % 100;
 		const uint8_t bcd_double_d = ((double_d / 10) * 16) + (double_d % 10);
-		XCTAssert(state.data[0] == bcd_double_d, "%02x + %02x = %02x; should equal %02x", bcd_d, bcd_d, state.data[0], bcd_double_d);
+		XCTAssert(state.registers.data[0] == bcd_double_d, "%02x + %02x = %02x; should equal %02x", bcd_d, bcd_d, state.registers.data[0], bcd_double_d);
 	}
 }
 
 - (void)testDivideByZero {
 	_machine->set_program({
-		0x7000,		// MOVE #0, D0;		location 0x400
-		0x3200,		// MOVE D0, D1;		location 0x402
+		0x7000,		// MOVE #0, D0;		location 0x1000
+		0x3200,		// MOVE D0, D1;		location 0x1002
 
-		0x82C0,		// DIVU;			location 0x404
+		0x82C0,		// DIVU;			location 0x1004
 
-		/* Next instruction would be at 0x406 */
-	});
-	_machine->set_initial_stack_pointer(0x1000);
+		/* Next instruction would be at 0x1006 */
+	}, 0x1000);
 
 	_machine->run_for_instructions(4);
 
 	const auto state = _machine->get_processor_state();
-	XCTAssert(state.supervisor_stack_pointer == 0x1000 - 6, @"Exception information should have been pushed to stack.");
+	XCTAssert(state.registers.supervisor_stack_pointer == 0x1000 - 6, @"Exception information should have been pushed to stack.");
 
-	const uint16_t *const stack_top = _machine->ram_at(state.supervisor_stack_pointer);
-	XCTAssert(stack_top[1] == 0x0000 && stack_top[2] == 0x1006, @"Return address should point to instruction after DIVU.");
+//	const uint16_t *const stack_top = _machine->ram_at(state.registers.supervisor_stack_pointer);
+//	XCTAssert(stack_top[1] == 0x0000 && stack_top[2] == 0x1006, @"Return address should point to instruction after DIVU.");
+	// TODO: determine whether above is a valid test; if so then it's suspicious that the exception
+	// is raised so as to avoid a final prefetch.
 }
 
 - (void)testMOVE {
@@ -177,28 +107,28 @@ class CPU::MC68000::ProcessorStorageTests {
 	// Perform MOVE #fb2e, D0
 	_machine->run_for_instructions(1);
 	auto state = _machine->get_processor_state();
-	XCTAssert(state.data[0] == 0xfb2e);
+	XCTAssert(state.registers.data[0] == 0xfb2e);
 
 	// Perform MOVE D0, D1
 	_machine->run_for_instructions(1);
 	state = _machine->get_processor_state();
-	XCTAssert(state.data[1] == 0xfb2e);
+	XCTAssert(state.registers.data[1] == 0xfb2e);
 
 	// Perform MOVEA D0, A0
 	_machine->run_for_instructions(1);
 	state = _machine->get_processor_state();
-	XCTAssert(state.address[0] == 0xfffffb2e, "A0 was %08x instead of 0xfffffb2e", state.address[0]);
+	XCTAssert(state.registers.address[0] == 0xfffffb2e, "A0 was %08x instead of 0xfffffb2e", state.registers.address[0]);
 
 	// Perform MOVEA.w (0x1000), A1
 	_machine->run_for_instructions(1);
 	state = _machine->get_processor_state();
-	XCTAssert(state.address[1] == 0x0000303c, "A1 was %08x instead of 0x0000303c", state.address[1]);
+	XCTAssert(state.registers.address[1] == 0x0000303c, "A1 was %08x instead of 0x0000303c", state.registers.address[1]);
 
 	// Perform MOVE #$400, A4; MOVE.l (A4), D2
 	_machine->run_for_instructions(2);
 	state = _machine->get_processor_state();
-	XCTAssert(state.address[4] == 0x1000, "A4 was %08x instead of 0x00001000", state.address[4]);
-	XCTAssert(state.data[2] == 0x303cfb2e, "D2 was %08x instead of 0x303cfb2e", state.data[2]);
+	XCTAssert(state.registers.address[4] == 0x1000, "A4 was %08x instead of 0x00001000", state.registers.address[4]);
+	XCTAssert(state.registers.data[2] == 0x303cfb2e, "D2 was %08x instead of 0x303cfb2e", state.registers.data[2]);
 }
 
 - (void)testVectoredInterrupt {
@@ -223,7 +153,7 @@ class CPU::MC68000::ProcessorStorageTests {
 	_machine->run_for_instructions(1);
 
 	const auto state = _machine->processor().get_state();
-	XCTAssertEqual(state.program_counter, 0x1008);	// i.e. the interrupt happened, the instruction performed was the one at 1004, and therefore
+	XCTAssertEqual(state.registers.program_counter, 0x1008);	// i.e. the interrupt happened, the instruction performed was the one at 1004, and therefore
 													// by the wonders of prefetch the program counter is now at 1008.
 }
 
@@ -287,7 +217,7 @@ class CPU::MC68000::ProcessorStorageTests {
 	XCTAssertEqual(_machine->get_cycle_count(), 6 + 2);
 }
 
-- (void)testOpcodeCoverage {
+/*- (void)testOpcodeCoverage {
 	// Perform an audit of implemented instructions.
 	CPU::MC68000::ProcessorStorageTests storage_tests(
 		_machine->processor(),
@@ -479,6 +409,6 @@ class CPU::MC68000::ProcessorStorageTests {
 	XCTAssert(!trimmedInvalids.count, "%@ opcodes should be valid but aren't: %@", @(trimmedInvalids.count), trimmedInvalids.hexDump);
 
 //	XCTAssert(!falseInvalids.count, "%@ opcodes should be valid but aren't: %@", @(falseInvalids.count), falseInvalids.hexDump);
-}
+}*/
 
 @end
diff --git a/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp b/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp
index 6c8c5472d..b85e97248 100644
--- a/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp	
+++ b/OSBindings/Mac/Clock SignalTests/Comparative68000.hpp	
@@ -11,9 +11,9 @@
 
 #include <zlib.h>
 
-#include "68000.hpp"
+#include "68000Mk2.hpp"
 
-class ComparativeBusHandler: public CPU::MC68000::BusHandler {
+class ComparativeBusHandler: public CPU::MC68000Mk2::BusHandler {
 	public:
 		ComparativeBusHandler(const char *trace_name) {
 			trace = gzopen(trace_name, "rt");
@@ -30,14 +30,14 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
 			++line_count;
 
 			// Generate state locally.
-			const auto state = get_state();
+			const auto state = get_state().registers;
 			char local_state[300];
 			sprintf(local_state, "%04x: %02x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x %08x\n",
 				address,
 				state.status,
 				state.data[0], state.data[1], state.data[2], state.data[3], state.data[4], state.data[5], state.data[6], state.data[7],
 				state.address[0], state.address[1], state.address[2], state.address[3], state.address[4], state.address[5], state.address[6],
-				(state.status & 0x2000) ? state.supervisor_stack_pointer : state.user_stack_pointer
+				state.stack_pointer()
 				);
 
 			// Check that the two coincide.
@@ -49,7 +49,7 @@ class ComparativeBusHandler: public CPU::MC68000::BusHandler {
 			}
 		}
 
-		virtual CPU::MC68000::ProcessorState get_state() = 0;
+		virtual CPU::MC68000Mk2::State get_state() = 0;
 
 	private:
 		int line_count = 0;
diff --git a/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm b/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm
index 978d6387e..2ac49ef95 100644
--- a/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/EmuTOSTests.mm	
@@ -13,7 +13,7 @@
 
 //#define LOG_TRACE
 
-#include "68000.hpp"
+#include "68000Mk2.hpp"
 #include "Comparative68000.hpp"
 #include "CSROMFetcher.hpp"
 
@@ -32,11 +32,11 @@ class EmuTOS: public ComparativeBusHandler {
 			m68000_.run_for(cycles);
 		}
 
-		CPU::MC68000::ProcessorState get_state() final {
+		CPU::MC68000Mk2::State get_state() final {
 			return m68000_.get_state();
 		}
 
-		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
+		HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
 			const uint32_t address = cycle.word_address();
 			uint32_t word_address = address;
 
@@ -56,7 +56,7 @@ class EmuTOS: public ComparativeBusHandler {
 				word_address %= ram_.size();
 			}
 
-			using Microcycle = CPU::MC68000::Microcycle;
+			using Microcycle = CPU::MC68000Mk2::Microcycle;
 			if(cycle.data_select_active()) {
 				uint16_t peripheral_result = 0xffff;
 				if(is_peripheral) {
@@ -72,16 +72,16 @@ class EmuTOS: public ComparativeBusHandler {
 					default: break;
 
 					case Microcycle::SelectWord | Microcycle::Read:
-						cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
+						cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
 					break;
 					case Microcycle::SelectByte | Microcycle::Read:
-						cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
+						cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
 					break;
 					case Microcycle::SelectWord:
-						base[word_address] = cycle.value->full;
+						base[word_address] = cycle.value->w;
 					break;
 					case Microcycle::SelectByte:
-						base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
+						base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
 					break;
 				}
 			}
@@ -90,7 +90,7 @@ class EmuTOS: public ComparativeBusHandler {
 		}
 
 	private:
-		CPU::MC68000::Processor<EmuTOS, true, true> m68000_;
+		CPU::MC68000Mk2::Processor<EmuTOS, true, true> m68000_;
 
 		std::vector<uint16_t> emuTOS_;
 		std::array<uint16_t, 256*1024> ram_;
diff --git a/OSBindings/Mac/Clock SignalTests/QLTests.mm b/OSBindings/Mac/Clock SignalTests/QLTests.mm
index 79f32f10c..d7d124d0c 100644
--- a/OSBindings/Mac/Clock SignalTests/QLTests.mm	
+++ b/OSBindings/Mac/Clock SignalTests/QLTests.mm	
@@ -35,11 +35,11 @@ class QL: public ComparativeBusHandler {
 			m68000_.run_for(cycles);
 		}
 
-		CPU::MC68000::ProcessorState get_state() final {
+		CPU::MC68000Mk2::State get_state() final {
 			return m68000_.get_state();
 		}
 
-		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
+		HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
 			const uint32_t address = cycle.word_address();
 			uint32_t word_address = address;
 
@@ -56,7 +56,7 @@ class QL: public ComparativeBusHandler {
 				word_address %= ram_.size();
 			}
 
-			using Microcycle = CPU::MC68000::Microcycle;
+			using Microcycle = CPU::MC68000Mk2::Microcycle;
 			if(cycle.data_select_active()) {
 				uint16_t peripheral_result = 0xffff;
 
@@ -64,18 +64,18 @@ class QL: public ComparativeBusHandler {
 					default: break;
 
 					case Microcycle::SelectWord | Microcycle::Read:
-						cycle.value->full = is_peripheral ? peripheral_result : base[word_address];
+						cycle.value->w = is_peripheral ? peripheral_result : base[word_address];
 					break;
 					case Microcycle::SelectByte | Microcycle::Read:
-						cycle.value->halves.low = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
+						cycle.value->b = (is_peripheral ? peripheral_result : base[word_address]) >> cycle.byte_shift();
 					break;
 					case Microcycle::SelectWord:
 						assert(!(is_rom && !is_peripheral));
-						if(!is_peripheral) base[word_address] = cycle.value->full;
+						if(!is_peripheral) base[word_address] = cycle.value->w;
 					break;
 					case Microcycle::SelectByte:
 						assert(!(is_rom && !is_peripheral));
-						if(!is_peripheral) base[word_address] = (cycle.value->halves.low << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
+						if(!is_peripheral) base[word_address] = (cycle.value->b << cycle.byte_shift()) | (base[word_address] & (0xffff ^ cycle.byte_mask()));
 					break;
 				}
 			}
@@ -84,7 +84,7 @@ class QL: public ComparativeBusHandler {
 		}
 
 	private:
-		CPU::MC68000::Processor<QL, true, true> m68000_;
+		CPU::MC68000Mk2::Processor<QL, true, false, true> m68000_;
 
 		std::vector<uint16_t> rom_;
 		std::array<uint16_t, 64*1024> ram_;
diff --git a/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp b/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp
index 061f1a0c8..71ab51199 100644
--- a/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp	
+++ b/OSBindings/Mac/Clock SignalTests/TestRunner68000.hpp	
@@ -10,104 +10,98 @@
 #define TestRunner68000_h
 
 #include <array>
+#include <functional>
+#include <vector>
 
-#include "../../../Processors/68000/68000.hpp"
+#include "../../../Processors/68000Mk2/68000Mk2.hpp"
 
-using Flag = CPU::MC68000::Flag;
+using namespace InstructionSet::M68k;
 
 /*!
 	Provides a 68000 with 64kb of RAM in its low address space;
 	/RESET will put the supervisor stack pointer at 0xFFFF and
 	begin execution at 0x0400.
 */
-class RAM68000: public CPU::MC68000::BusHandler {
+class RAM68000: public CPU::MC68000Mk2::BusHandler {
 	public:
-		RAM68000() : m68000_(*this) {
-			// Setup the /RESET vector.
-			ram_[0] = 0;
-			ram_[1] = 0x206;	// Supervisor stack pointer.
-			ram_[2] = 0;
-			ram_[3] = 0x1000;	// Initial PC.
-
-			// Ensure the condition codes start unset.
-			auto state = get_processor_state();
-			state.status &= ~Flag::ConditionCodes;
-			set_processor_state(state);
-		}
+		RAM68000() : m68000_(*this) {}
 
 		uint32_t initial_pc() const {
 			return 0x1000;
 		}
 
-		void set_program(const std::vector<uint16_t> &program) {
+		void set_program(
+			const std::vector<uint16_t> &program,
+			uint32_t stack_pointer = 0x206
+		) {
 			memcpy(&ram_[0x1000 >> 1], program.data(), program.size() * sizeof(uint16_t));
 
-			// Add a NOP suffix, to avoid corrupting flags should the attempt to
-			// run for a certain number of instructions overrun.
-			ram_[(0x1000 >> 1) + program.size()] = 0x4e71;
+			// Ensure the condition codes start unset and set the initial program counter
+			// and supervisor stack pointer, as well as starting in supervisor mode.
+			auto registers = m68000_.get_state().registers;
+			registers.status = 0x2700;
+			registers.program_counter = initial_pc();
+			registers.supervisor_stack_pointer = stack_pointer;
+			m68000_.decode_from_state(registers);
 		}
 
-		void set_initial_stack_pointer(uint32_t sp) {
-			ram_[0] = sp >> 16;
-			ram_[1] = sp & 0xffff;
+		void set_registers(std::function<void(InstructionSet::M68k::RegisterSet &)> func) {
+			auto state = m68000_.get_state();
+			func(state.registers);
+			m68000_.set_state(state);
 		}
 
 		void will_perform(uint32_t, uint16_t) {
 			--instructions_remaining_;
+			if(instructions_remaining_ < 0) {
+				throw StopException();
+			}
 		}
 
 		void run_for_instructions(int count) {
-			instructions_remaining_ = count + (has_run_ ? 0 : 1);
-			finish_reset_if_needed();
+			duration_ = HalfCycles(0);
+			instructions_remaining_ = count;
+			if(!instructions_remaining_) return;
 
-			while(instructions_remaining_) {
-				run_for(HalfCycles(2));
-			}
+			try {
+				while(true) {
+					run_for(HalfCycles(2000));
+				}
+			} catch (const StopException &) {}
 		}
 
 		void run_for(HalfCycles cycles) {
-			finish_reset_if_needed();
 			m68000_.run_for(cycles);
 		}
 
-		void finish_reset_if_needed() {
-			// If the 68000 hasn't run yet, build in the necessary
-			// cycles to finish the reset program, and set the stored state.
-			if(!has_run_) {
-				has_run_ = true;
-				m68000_.run_for(HalfCycles(76));
-				duration_ -= HalfCycles(76);
-			}
-		}
-
 		uint16_t *ram_at(uint32_t address) {
 			return &ram_[(address >> 1) % ram_.size()];
 		}
 
-		HalfCycles perform_bus_operation(const CPU::MC68000::Microcycle &cycle, int) {
+		HalfCycles perform_bus_operation(const CPU::MC68000Mk2::Microcycle &cycle, int) {
 			const uint32_t word_address = cycle.word_address();
-			if(instructions_remaining_) duration_ += cycle.length;
+			duration_ += cycle.length;
 
-			using Microcycle = CPU::MC68000::Microcycle;
+			using Microcycle = CPU::MC68000Mk2::Microcycle;
 			if(cycle.data_select_active()) {
 				if(cycle.operation & Microcycle::InterruptAcknowledge) {
-					cycle.value->halves.low = 10;
+					cycle.value->b = 10;
 				} else {
 					switch(cycle.operation & (Microcycle::SelectWord | Microcycle::SelectByte | Microcycle::Read)) {
 						default: break;
 
 						case Microcycle::SelectWord | Microcycle::Read:
-							cycle.value->full = ram_[word_address % ram_.size()];
+							cycle.value->w = ram_[word_address % ram_.size()];
 						break;
 						case Microcycle::SelectByte | Microcycle::Read:
-							cycle.value->halves.low = ram_[word_address % ram_.size()] >> cycle.byte_shift();
+							cycle.value->b = ram_[word_address % ram_.size()] >> cycle.byte_shift();
 						break;
 						case Microcycle::SelectWord:
-							ram_[word_address % ram_.size()] = cycle.value->full;
+							ram_[word_address % ram_.size()] = cycle.value->w;
 						break;
 						case Microcycle::SelectByte:
 							ram_[word_address % ram_.size()] = uint16_t(
-								(cycle.value->halves.low << cycle.byte_shift()) |
+								(cycle.value->b << cycle.byte_shift()) |
 								(ram_[word_address % ram_.size()] & cycle.untouched_byte_mask())
 							);
 						break;
@@ -118,15 +112,11 @@ class RAM68000: public CPU::MC68000::BusHandler {
 			return HalfCycles(0);
 		}
 
-		CPU::MC68000::Processor<RAM68000, true>::State get_processor_state() {
+		CPU::MC68000Mk2::State get_processor_state() {
 			return m68000_.get_state();
 		}
 
-		void set_processor_state(const CPU::MC68000::Processor<RAM68000, true>::State &state) {
-			m68000_.set_state(state);
-		}
-
-		CPU::MC68000::Processor<RAM68000, true, true> &processor() {
+		auto &processor() {
 			return m68000_;
 		}
 
@@ -139,11 +129,12 @@ class RAM68000: public CPU::MC68000::BusHandler {
 		}
 
 	private:
-		CPU::MC68000::Processor<RAM68000, true, true> m68000_;
+		struct StopException {};
+
+		CPU::MC68000Mk2::Processor<RAM68000, true, true, true> m68000_;
 		std::array<uint16_t, 256*1024> ram_{};
 		int instructions_remaining_;
 		HalfCycles duration_;
-		bool has_run_ = false;
 };
 
 #endif /* TestRunner68000_h */
diff --git a/Processors/68000Mk2/68000Mk2.hpp b/Processors/68000Mk2/68000Mk2.hpp
new file mode 100644
index 000000000..f58777494
--- /dev/null
+++ b/Processors/68000Mk2/68000Mk2.hpp
@@ -0,0 +1,453 @@
+//
+//  68000Mk2.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 16/05/2022.
+//  Copyright © 2022 Thomas Harte. All rights reserved.
+//
+
+#ifndef _8000Mk2_h
+#define _8000Mk2_h
+
+#include "../../ClockReceiver/ClockReceiver.hpp"
+#include "../../Numeric/RegisterSizes.hpp"
+#include "../../InstructionSets/M68k/RegisterSet.hpp"
+
+namespace CPU {
+namespace MC68000Mk2 {
+
+/*!
+	A microcycle is an atomic unit of 68000 bus activity — it is a single item large enough
+	fully to specify a sequence of bus events that occur without any possible interruption.
+
+	Concretely, a standard read cycle breaks down into at least two microcycles:
+
+		1) a 4 half-cycle length microcycle in which the address strobe is signalled; and
+		2) a 4 half-cycle length microcycle in which at least one of the data strobes is
+		signalled, and the data bus is sampled.
+
+	That is, assuming DTack were signalled when microcycle (1) ended. If not then additional
+	wait state microcycles would fall between those two parts.
+
+	The 68000 data sheet defines when the address becomes valid during microcycle (1), and
+	when the address strobe is actually asserted. But those timings are fixed. So simply
+	telling you that this was a microcycle during which the address trobe was signalled is
+	sufficient fully to describe the bus activity.
+
+	(Aside: see the 68000 template's definition for options re: implicit DTack; if your
+	68000 owner can always predict exactly how long it will hold DTack following observation
+	of an address-strobing microcycle, it can just supply those periods for accounting and
+	avoid the runtime cost of actual DTack emulation. But such as the bus allows.)
+*/
+struct Microcycle {
+	using OperationT = unsigned int;
+
+	/// Indicates that the address strobe and exactly one of the data strobes are active; you can determine
+	/// which by inspecting the low bit of the provided address. The RW line indicates a read.
+	static constexpr OperationT SelectByte				= 1 << 0;
+	// Maintenance note: this is bit 0 to reduce the cost of getting a host-endian
+	// bytewise address. The assumption that it is bit 0 is also used for branchless
+	// selection in a few places. See implementation of host_endian_byte_address(),
+	// value8_high(), value8_low() and value16().
+
+	/// Indicates that the address and both data select strobes are active.
+	static constexpr OperationT SelectWord				= 1 << 1;
+
+	/// If set, indicates a read. Otherwise, a write.
+	static constexpr OperationT Read 					= 1 << 2;
+
+	// Two-bit gap deliberately left here for PermitRead/Write below.
+
+	/// A NewAddress cycle is one in which the address strobe is initially low but becomes high;
+	/// this correlates to states 0 to 5 of a standard read/write cycle.
+	static constexpr OperationT NewAddress				= 1 << 5;
+
+	/// A SameAddress cycle is one in which the address strobe is continuously asserted, but neither
+	/// of the data strobes are.
+	static constexpr OperationT SameAddress				= 1 << 6;
+
+	/// A Reset cycle is one in which the RESET output is asserted.
+	static constexpr OperationT Reset					= 1 << 7;
+
+	/// Contains the value of line FC0 if it is not implicit via InterruptAcknowledge.
+	static constexpr OperationT IsData 					= 1 << 8;
+
+	/// Contains the value of line FC1 if it is not implicit via InterruptAcknowledge.
+	static constexpr OperationT IsProgram 				= 1 << 9;
+
+	/// The interrupt acknowledge cycle is that during which the 68000 seeks to obtain the vector for
+	/// an interrupt it plans to observe. Noted on a real 68000 by all FCs being set to 1.
+	static constexpr OperationT InterruptAcknowledge	= 1 << 10;
+
+	/// Represents the state of the 68000's valid memory address line — indicating whether this microcycle
+	/// is synchronised with the E clock to satisfy a valid peripheral address request.
+	static constexpr OperationT IsPeripheral 			= 1 << 11;
+
+	/// Provides the 68000's bus grant line — indicating whether a bus request has been acknowledged.
+	static constexpr OperationT BusGrant				= 1 << 12;
+
+	/// Contains a valid combination of the various static constexpr int flags, describing the operation
+	/// performed by this Microcycle.
+	OperationT operation = 0;
+
+	/// Describes the duration of this Microcycle.
+	HalfCycles length = HalfCycles(4);
+
+	/*!
+		For expediency, this provides a full 32-bit byte-resolution address — e.g.
+		if reading indirectly via an address register, this will indicate the full
+		value of the address register.
+
+		The receiver should ignore bits 0 and 24+. Use word_address() automatically
+		to obtain the only the 68000's real address lines, giving a 23-bit address
+		at word resolution.
+	*/
+	const uint32_t *address = nullptr;
+
+	/*!
+		If this is a write cycle, dereference value to get the value loaded onto
+		the data bus.
+
+		If this is a read cycle, write the value on the data bus to it.
+
+		Otherwise, this value is undefined.
+
+		If this bus cycle provides a byte then its value is provided via
+		@c value->b and @c value->w is undefined. This is true regardless of
+		whether the upper or lower byte of a word is being accessed.
+
+		Word values occupy the entirety of @c value->w.
+	*/
+	SlicedInt16 *value = nullptr;
+
+	Microcycle(OperationT operation) : operation(operation) {}
+	Microcycle(OperationT operation, HalfCycles length) : operation(operation), length(length) {}
+	Microcycle() {}
+
+	/// @returns @c true if two Microcycles are equal; @c false otherwise.
+	bool operator ==(const Microcycle &rhs) const {
+		if(value != rhs.value) return false;
+		if(address != rhs.address) return false;
+		if(length != rhs.length) return false;
+		if(operation != rhs.operation) return false;
+		return true;
+	}
+
+	// Various inspectors.
+
+	/*! @returns true if any data select line is active; @c false otherwise. */
+	forceinline bool data_select_active() const {
+		return bool(operation & (SelectWord | SelectByte | InterruptAcknowledge));
+	}
+
+	/*!
+		@returns 0 if this byte access wants the low part of a 16-bit word; 8 if it wants the high part.
+	*/
+	forceinline unsigned int byte_shift() const {
+		return (((*address) & 1) << 3) ^ 8;
+	}
+
+	/*!
+		Obtains the mask to apply to a word that will leave only the byte this microcycle is selecting.
+
+		@returns 0x00ff if this byte access wants the low part of a 16-bit word; 0xff00 if it wants the high part.
+	*/
+	forceinline uint16_t byte_mask() const {
+		return uint16_t(0xff00) >> (((*address) & 1) << 3);
+	}
+
+	/*!
+		Obtains the mask to apply to a word that will leave only the byte this microcycle **isn't** selecting.
+		i.e. this is the part of a word that should be untouched by this microcycle.
+
+		@returns 0xff00 if this byte access wants the low part of a 16-bit word; 0x00ff if it wants the high part.
+	*/
+	forceinline uint16_t untouched_byte_mask() const {
+		return uint16_t(uint16_t(0xff) << (((*address) & 1) << 3));
+	}
+
+	/*!
+		Assuming this cycle is a byte write, mutates @c destination by writing the byte to the proper upper or
+		lower part, retaining the other half.
+	*/
+	forceinline uint16_t write_byte(uint16_t destination) const {
+		return uint16_t((destination & untouched_byte_mask()) | (value->b << byte_shift()));
+	}
+
+	/*!
+		@returns non-zero if this is a byte read and 68000 LDS is asserted.
+	*/
+	forceinline int lower_data_select() const {
+		return (operation & SelectByte) & ((*address & 1) << 3);
+	}
+
+	/*!
+		@returns non-zero if this is a byte read and 68000 UDS is asserted.
+	*/
+	forceinline int upper_data_select() const {
+		return (operation & SelectByte) & ~((*address & 1) << 3);
+	}
+
+	/*!
+		@returns the address being accessed at the precision a 68000 supplies it —
+		only 24 address bit precision, with the low bit shifted out. So it's the
+		68000 address at word precision: address 0 is the first word in the address
+		space, address 1 is the second word (i.e. the third and fourth bytes) in
+		the address space, etc.
+	*/
+	forceinline uint32_t word_address() const {
+		return (address ? (*address) & 0x00fffffe : 0) >> 1;
+	}
+
+	/*!
+		@returns the address of the word or byte being accessed at byte precision,
+		in the endianness of the host platform.
+
+		So: if this is a word access, and the 68000 wants to select the word at address
+		@c n, this will evaluate to @c n regardless of the host machine's endianness..
+
+		If this is a byte access and the host machine is big endian it will evalue to @c n.
+
+		If the host machine is little endian then it will evaluate to @c n^1.
+	*/
+	forceinline uint32_t host_endian_byte_address() const {
+		#if TARGET_RT_BIG_ENDIAN
+		return *address & 0xffffff;
+		#else
+		return (*address ^ (1 & operation & SelectByte)) & 0xffffff;
+		#endif
+	}
+
+	/*!
+		@returns the value on the data bus — all 16 bits, with any inactive lines
+		(as er the upper and lower data selects) being represented by 1s. Assumes
+		this is a write cycle.
+	*/
+	forceinline uint16_t value16() const {
+		const uint16_t values[] = { value->w, uint16_t((value->b << 8) | value->b) };
+		return values[operation & SelectByte];
+	}
+
+	/*!
+		@returns the value currently on the high 8 lines of the data bus if any;
+		@c 0xff otherwise. Assumes this is a write cycle.
+	*/
+	forceinline uint8_t value8_high() const {
+		const uint8_t values[] = { uint8_t(value->w), value->b};
+		return values[operation & SelectByte];
+	}
+
+	/*!
+		@returns the value currently on the low 8 lines of the data bus if any;
+		@c 0xff otherwise. Assumes this is a write cycle.
+	*/
+	forceinline uint8_t value8_low() const {
+		const uint8_t values[] = { uint8_t(value->w), value->b};
+		return values[operation & SelectByte];
+	}
+
+	/*!
+		Sets to @c value the 8- or 16-bit portion of the supplied value that is
+		currently being read. Assumes this is a read cycle.
+	*/
+	forceinline void set_value16(uint16_t v) const {
+		assert(operation & Microcycle::Read);
+		if(operation & Microcycle::SelectWord) {
+			value->w = v;
+		} else {
+			value->b = uint8_t(v >> byte_shift());
+		}
+	}
+
+	/*!
+		Equivalent to set_value16((v << 8) | 0x00ff).
+	*/
+	forceinline void set_value8_high(uint8_t v) const {
+		assert(operation & Microcycle::Read);
+		if(operation & Microcycle::SelectWord) {
+			value->w = uint16_t(0x00ff | (v << 8));
+		} else {
+			value->b = uint8_t(v | (0xff00 >> ((*address & 1) << 3)));
+		}
+	}
+
+	/*!
+		Equivalent to set_value16((v) | 0xff00).
+	*/
+	forceinline void set_value8_low(uint8_t v) const {
+		assert(operation & Microcycle::Read);
+		if(operation & Microcycle::SelectWord) {
+			value->w = 0xff00 | v;
+		} else {
+			value->b = uint8_t(v | (0x00ff << ((*address & 1) << 3)));
+		}
+	}
+
+	/*!
+		@returns the same value as word_address() for any Microcycle with the NewAddress or
+		SameAddress flags set; undefined behaviour otherwise.
+	*/
+	forceinline uint32_t active_operation_word_address() const {
+		return ((*address) & 0x00fffffe) >> 1;
+	}
+
+	// PermitRead and PermitWrite are used as part of the read/write mask
+	// supplied to @c apply; they are picked to be small enough values that
+	// a byte can be used for storage.
+	static constexpr OperationT PermitRead 	= 1 << 3;
+	static constexpr OperationT PermitWrite	= 1 << 4;
+
+	/*!
+		Assuming this to be a cycle with a data select active, applies it to @c target
+		subject to the read_write_mask, where 'applies' means:
+
+			* if this is a byte read, reads a single byte from @c target;
+			* if this is a word read, reads a word (in the host platform's endianness) from @c target; and
+			* if this is a write, does the converse of a read.
+	*/
+	forceinline void apply(uint8_t *target, OperationT read_write_mask = PermitRead | PermitWrite) const {
+		assert( (operation & (SelectWord | SelectByte)) != (SelectWord | SelectByte));
+
+		switch((operation | read_write_mask) & (SelectWord | SelectByte | Read | PermitRead | PermitWrite)) {
+			default:
+			break;
+
+			case SelectWord | Read | PermitRead:
+			case SelectWord | Read | PermitRead | PermitWrite:
+				value->w = *reinterpret_cast<uint16_t *>(target);
+			break;
+			case SelectByte | Read | PermitRead:
+			case SelectByte | Read | PermitRead | PermitWrite:
+				value->b = *target;
+			break;
+			case SelectWord | PermitWrite:
+			case SelectWord | PermitWrite | PermitRead:
+				*reinterpret_cast<uint16_t *>(target) = value->w;
+			break;
+			case SelectByte | PermitWrite:
+			case SelectByte | PermitWrite | PermitRead:
+				*target = value->b;
+			break;
+		}
+	}
+};
+
+/*!
+	This is the prototype for a 68000 bus handler; real bus handlers can descend from this
+	in order to get default implementations of any changes that may occur in the expected interface.
+*/
+class BusHandler {
+	public:
+		/*!
+			Provides the bus handler with a single Microcycle to 'perform'.
+
+			FC0 and FC1 are provided inside the microcycle as the IsData and IsProgram
+			flags; FC2 is provided here as is_supervisor — it'll be either 0 or 1.
+		*/
+		HalfCycles perform_bus_operation([[maybe_unused]] const Microcycle &cycle, [[maybe_unused]] int is_supervisor) {
+			return HalfCycles(0);
+		}
+
+		void flush() {}
+
+		/*!
+			Provides information about the path of execution if enabled via the template.
+		*/
+		void will_perform([[maybe_unused]] uint32_t address, [[maybe_unused]] uint16_t opcode) {}
+};
+
+struct State {
+	InstructionSet::M68k::RegisterSet registers;
+};
+
+}
+}
+
+#include "Implementation/68000Mk2Storage.hpp"
+
+namespace CPU {
+namespace MC68000Mk2 {
+
+/*!
+	Provides an emulation of the 68000 with accurate bus logic via the @c BusHandler, subject to the following template parameters:
+
+	@c dtack_is_implicit means that the 68000 won't wait around for DTACK during any data access. BERR or VPA may still be
+		signalled at the appropriate moment and will override the implicit DTACK, but the processor won't spin if nothing is explicitly
+		signalled. Enabling this simplifies the internal state machine and therefore improves performance; bus handlers can still indicate
+		that time was spent waiting for DTACK by returning an appropriate value from @c perform_bus_operation.
+
+	@c permit_overrun allows the 68000 to be relaxed in how it interprets the constraint specified by the @c duration parameter to
+		@c run_for. If this is @c false, @c run_for will always return as soon as it has called @c perform_bus_operation with whichever
+		operation is ongoing at the requested stopping time. If it is @c true then the 68000 is granted leeway to overrun the requested stop
+		time by 'a small amount' as and when it is a benefit to do so. Any overrun will be subtracted from the next @c run_for.
+
+		In practice this allows the implementation to avoid a bunch of conditional checks by considering whether it needs to exit less frequently.
+
+		Teleologically, it's expected that most — if not all — single-processor machines can permit overruns for a performance boost with
+		no user-visible difference.
+
+	@c signal_will_perform indicates whether the 68000 will call the bus handler's @c will_perform. Unlike the popular 8-bit CPUs,
+		the 68000 doesn't offer an indication of when instruction dispatch will occur so this is provided *for testing purposes*. It allows test cases
+		to track execution and inspect internal state in a wholly unrealistic fashion.
+*/
+template <class BusHandler, bool dtack_is_implicit = true, bool permit_overrun = true, bool signal_will_perform = false>
+class Processor: private ProcessorBase {
+	public:
+		Processor(BusHandler &bus_handler) : ProcessorBase(), bus_handler_(bus_handler) {}
+
+		void run_for(HalfCycles duration);
+
+		/// @returns The current processor state.
+		CPU::MC68000Mk2::State get_state();
+
+		/// Sets the current processor state.
+		void set_state(const CPU::MC68000Mk2::State &);
+
+		/// Sets all registers to the values provided, fills the prefetch queue and ensures the
+		/// next action the processor will take is to decode whatever is in the queue.
+		///
+		/// The queue is filled synchronously, during this call, causing calls to the bus handler.
+		void decode_from_state(const InstructionSet::M68k::RegisterSet &);
+
+		// TODO: bus ack/grant, halt,
+
+		/// Sets the DTack line — @c true for active, @c false for inactive.
+		inline void set_dtack(bool dtack) {
+			dtack_ = dtack;
+		}
+
+		/// Sets the VPA (valid peripheral address) line — @c true for active, @c false for inactive.
+		inline void set_is_peripheral_address(bool is_peripheral_address) {
+			vpa_ = is_peripheral_address;
+		}
+
+		/// Sets the bus error line — @c true for active, @c false for inactive.
+		inline void set_bus_error(bool bus_error) {
+			berr_ = bus_error;
+		}
+
+		/// Sets the interrupt lines, IPL0, IPL1 and IPL2.
+		inline void set_interrupt_level(int interrupt_level) {
+			bus_interrupt_level_ = interrupt_level;
+		}
+
+		/// @returns The current phase of the E clock; this will be a number of
+		/// half-cycles between 0 and 19 inclusive, indicating how far the 68000
+		/// is into the current E cycle.
+		///
+		/// This is guaranteed to be 0 at initial 68000 construction. It is not guaranteed
+		/// to return the correct result if called during a bus transaction.
+		HalfCycles get_e_clock_phase() {
+			return e_clock_phase_;
+		}
+
+	private:
+		BusHandler &bus_handler_;
+};
+
+}
+}
+
+#include "Implementation/68000Mk2Implementation.hpp"
+
+#endif /* _8000Mk2_h */
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
new file mode 100644
index 000000000..ca64c3feb
--- /dev/null
+++ b/Processors/68000Mk2/Implementation/68000Mk2Implementation.hpp
@@ -0,0 +1,2787 @@
+//
+//  68000Mk2Implementation.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 16/05/2022.
+//  Copyright © 2022 Thomas Harte. All rights reserved.
+//
+
+#ifndef _8000Mk2Implementation_h
+#define _8000Mk2Implementation_h
+
+#include <cassert>
+#include <cstdio>
+
+#include "../../../InstructionSets/M68k/ExceptionVectors.hpp"
+
+namespace CPU {
+namespace MC68000Mk2 {
+
+/// States for the state machine which are named by
+/// me for their purpose rather than automatically by file position.
+/// These are negative to avoid ambiguity with the other group.
+enum ExecutionState: int {
+	Reset			= std::numeric_limits<int>::min(),
+	Decode,
+	WaitForDTACK,
+
+	/// Perform the proper sequence to fetch a byte or word operand.
+	FetchOperand_bw,
+	/// Perform the proper sequence to fetch a long-word operand.
+	FetchOperand_l,
+
+	StoreOperand,
+	StoreOperand_bw,
+	StoreOperand_l,
+
+	StandardException,
+	BusOrAddressErrorException,
+	DoInterrupt,
+
+	// Specific addressing mode fetches.
+	//
+	// Additional context here is that I'm very much on the fence but
+	// for now am telling myself:
+	//
+	//	(1)	the overwhelming majority of instructions that need an
+	//		effective address calculation use it for an operand read
+	//		immediately afterwards, so keeping those things bound
+	//		avoids a large number of conditional branches; and
+	//	(2)	making a decision between byte/word and long-word once at
+	//		the outset also saves a conditional for any two-operand
+	//		instructions (which is also the majority); but
+	//	(3)	some instructions do just need the address calculation —
+	//		LEA and PEA are obvious examples, but are not the
+	//		exhaustive list — so a third route just to do the
+	//		calculation is necessary.
+	//
+	// My internal dialogue then argues that each of these is actually
+	// a small amount of code, so the need manually to duplicate (per
+	// the control-flow constraints of using a switch as a coroutine)
+	// isn't too ugly. Possibly even less ugly than pulling things out
+	// with a macro, especially for debugging.
+	//
+	// Further consideration may be necessary. Especially once this is
+	// up on its feet and profiling becomes an option.
+
+	FetchAddressRegisterIndirect_bw,
+	FetchAddressRegisterIndirectWithPostincrement_bw,
+	FetchAddressRegisterIndirectWithPredecrement_bw,
+	FetchAddressRegisterIndirectWithDisplacement_bw,
+	FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw,
+	FetchProgramCounterIndirectWithDisplacement_bw,
+	FetchProgramCounterIndirectWithIndex8bitDisplacement_bw,
+	FetchAbsoluteShort_bw,
+	FetchAbsoluteLong_bw,
+	FetchImmediateData_bw,
+
+	FetchAddressRegisterIndirect_l,
+	FetchAddressRegisterIndirectWithPostincrement_l,
+	FetchAddressRegisterIndirectWithPredecrement_l,
+	FetchAddressRegisterIndirectWithDisplacement_l,
+	FetchAddressRegisterIndirectWithIndex8bitDisplacement_l,
+	FetchProgramCounterIndirectWithDisplacement_l,
+	FetchProgramCounterIndirectWithIndex8bitDisplacement_l,
+	FetchAbsoluteShort_l,
+	FetchAbsoluteLong_l,
+	FetchImmediateData_l,
+
+	CalcEffectiveAddress,											// -
+	CalcAddressRegisterIndirect,									// -
+	CalcAddressRegisterIndirectWithPostincrement,					// -
+	CalcAddressRegisterIndirectWithPredecrement,					// -
+	CalcAddressRegisterIndirectWithDisplacement,					// np
+	CalcAddressRegisterIndirectWithIndex8bitDisplacement,			// np n
+	CalcProgramCounterIndirectWithDisplacement,						// np
+	CalcProgramCounterIndirectWithIndex8bitDisplacement,			// np n
+	CalcAbsoluteShort,												// np
+	CalcAbsoluteLong,												// np np
+
+	CalcEffectiveAddressIdleFor8bitDisplacement,					// As per CalcEffectiveAddress unless one of the
+																	// 8-bit displacement modes is in use, in which case
+																	// an extra idle bus state is prefixed.
+
+	// Various forms of perform; each of these will
+	// perform the current instruction, then do the
+	// indicated bus cycle.
+
+	Perform_np,
+	Perform_np_n,
+	Perform_np_nn,
+
+	MOVE,
+	MOVE_predec,
+	MOVE_predec_l,
+	MOVE_prefetch_decode,
+	MOVE_complete,
+	MOVE_complete_l,
+
+	TwoOp_Predec_bw,
+	TwoOp_Predec_l,
+
+	CHK,
+	CHK_no_trap,
+	CHK_was_over,
+	CHK_was_under,
+
+	Scc_Dn,
+	Scc_Dn_did_not_set,
+	Scc_Dn_did_set,
+
+	DBcc,
+	DBcc_branch_taken,
+	DBcc_condition_true,
+	DBcc_counter_overflow,
+
+	Bccb,
+	Bccw,
+	Bcc_branch_taken,
+	Bccb_branch_not_taken,
+	Bccw_branch_not_taken,
+
+	BSRb,
+	BSRw,
+
+	JSRJMPAddressRegisterIndirect,
+	JSRJMPAddressRegisterIndirectWithDisplacement,
+	JSRJMPAddressRegisterIndirectWithIndex8bitDisplacement,
+	JSRJMPProgramCounterIndirectWithDisplacement,
+	JSRJMPProgramCounterIndirectWithIndex8bitDisplacement,
+	JSRJMPAbsoluteShort,
+	JSRJMPAbsoluteLong,
+
+	JSR, JMP,
+
+	BCHG_BSET_Dn,
+	BCLR_Dn,
+
+	MOVEPtoM_w,
+	MOVEPtoM_l,
+	MOVEPtoR_w,
+	MOVEPtoR_l,
+
+	LogicalToSR,
+
+	MOVEMtoR, MOVEMtoR_l_read, MOVEMtoR_w_read, MOVEMtoR_finish,
+	MOVEMtoM,
+		MOVEMtoM_l_write, MOVEMtoM_w_write,
+		MOVEMtoM_l_write_predec, MOVEMtoM_w_write_predec,
+	MOVEMtoM_finish,
+
+	DIVU_DIVS,
+	Perform_idle_dyamic_Dn,
+	LEA,
+	PEA,
+	TAS,
+	MOVEtoCCRSR,
+	RTR,
+	RTE,
+	RTS,
+	LINKw,
+	UNLINK,
+	RESET,
+	NOP,
+	STOP,
+	TRAP,
+	TRAPV,
+};
+
+// MARK: - The state machine.
+
+template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
+void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::run_for(HalfCycles duration) {
+	// Accumulate the newly paid-in cycles. If this instance remains in deficit, exit.
+	e_clock_phase_ += duration;
+	time_remaining_ += duration;
+	if(time_remaining_ < HalfCycles(0)) return;
+
+	// Check whether all remaining time has been expended; if so then exit, having set this line up as
+	// the next resumption point.
+#define ConsiderExit()	if(time_remaining_ < HalfCycles(0)) { state_ = __COUNTER__+1; return; } [[fallthrough]]; case __COUNTER__:
+
+	// Subtracts `n` half-cycles from `time_remaining_`; if permit_overrun is false, also ConsiderExit()
+#define Spend(n)		time_remaining_ -= (n); if constexpr (!permit_overrun) ConsiderExit()
+
+	// Performs ConsiderExit() only if permit_overrun is true.
+#define CheckOverrun()	if constexpr (permit_overrun) ConsiderExit()
+
+	// Moves directly to state x, which must be a compile-time constant.
+#define MoveToStateSpecific(x)	goto x;
+
+	// Moves to state x by dynamic dispatch; x can be a regular variable.
+#define MoveToStateDynamic(x)	{ state_ = x; continue; }
+
+	// Sets the start position for state x.
+#define BeginState(x)	case ExecutionState::x: [[maybe_unused]] x
+
+	//
+	// So basic structure is, in general:
+	//
+	//	BeginState(Action):
+	//		do_something();
+	//		Spend(20);
+	//		do_something_else();
+	//		Spend(10);
+	//		do_a_third_thing();
+	//		Spend(30);
+	//	MoveToState(next_action);
+	//
+	// Additional notes:
+	//
+	//	Action and all equivalents should be negative values, since the
+	//	switch-for-computed-goto-for-a-coroutine structure uses __COUNTER__* for
+	//	its invented entry- and exit-points, meaning that negative numbers are
+	//	the easiest group that is safely definitely never going to collide.
+	//
+	//	(* an extension supported by at least GCC, Clang and MSVC)
+
+
+	// Spare containers:
+	HalfCycles delay;		// To receive any additional time added on by calls to perform_bus_operation.
+
+	// Helper macros for common bus transactions:
+
+	// Performs the bus operation and then applies a `Spend` of its length
+	// plus any additional length returned by the bus handler.
+#define PerformBusOperation(x)										\
+	delay = bus_handler_.perform_bus_operation(x, is_supervisor_);	\
+	Spend(x.length + delay)
+
+	// Performs no bus activity for the specified number of microcycles.
+#define IdleBus(n)						\
+	idle.length = HalfCycles((n) << 2);	\
+	PerformBusOperation(idle)
+
+	// Spin until DTACK, VPA or BERR is asserted (unless DTACK is implicit),
+	// holding the bus cycle provided.
+#define WaitForDTACK(x)													\
+	if constexpr (!dtack_is_implicit && !dtack_ && !vpa_ && !berr_) {	\
+		awaiting_dtack = x;												\
+		awaiting_dtack.length = HalfCycles(2);							\
+		post_dtack_state_ = __COUNTER__+1;								\
+		state_ = ExecutionState::WaitForDTACK;							\
+		break;															\
+	}																	\
+	[[fallthrough]]; case __COUNTER__:
+
+	// Performs the bus operation provided, which will be one with a
+	// SelectWord or SelectByte operation, stretching it to match the E
+	// bus if VPA is currently asserted or seguing elsewhere if a bus
+	// error is signalled or an adress error observed.
+	//
+	// E clock behaviour implemented, which I think is correct:
+	//
+	//	(1) wait until end of current 10-cycle window;
+	//	(2) run for the next 10-cycle window.
+#define CompleteAccess(x)												\
+	if(berr_ || (*x.address & (x.operation >> 1) & 1)) {				\
+		bus_error_ = x;													\
+		exception_vector_ = berr_ ? InstructionSet::M68k::AccessFault : InstructionSet::M68k::AddressError;	\
+		MoveToStateSpecific(BusOrAddressErrorException);				\
+	}																	\
+	if(vpa_) {															\
+		x.length = HalfCycles(20) + (HalfCycles(20) + (e_clock_phase_ - time_remaining_) % HalfCycles(20)) % HalfCycles(20);	\
+	} else {															\
+		x.length = HalfCycles(4);										\
+	}																	\
+	PerformBusOperation(x)
+
+	// Performs the memory access implied by the announce, perform pair,
+	// honouring DTACK, BERR and VPA as necessary.
+#define AccessPair(val, announce, perform)			\
+	perform.value = &val;							\
+	if constexpr (!dtack_is_implicit) {				\
+		announce.length = HalfCycles(4);			\
+	}												\
+	PerformBusOperation(announce);					\
+	WaitForDTACK(announce);							\
+	CompleteAccess(perform);
+
+	// Sets up the next data access size and read flags.
+#define SetupDataAccess(read_flag, select_flag)												\
+	access_announce.operation = Microcycle::NewAddress | Microcycle::IsData | (read_flag);	\
+	access.operation = access_announce.operation | (select_flag);
+
+	// Sets the address source for the next data access.
+#define SetDataAddress(addr)							\
+	access.address = access_announce.address = &addr;
+
+	// Performs the access established by SetupDataAccess into val.
+#define Access(val)										\
+	AccessPair(val, access_announce, access)
+
+	// Reads the program (i.e. non-data) word from addr into val.
+#define ReadProgramWord(val)								\
+	AccessPair(val, read_program_announce, read_program);	\
+	program_counter_.l += 2;
+
+	// Reads one futher word from the program counter and inserts it into
+	// the prefetch queue.
+#define Prefetch()										\
+	captured_interrupt_level_ = bus_interrupt_level_;	\
+	prefetch_.high = prefetch_.low;						\
+	ReadProgramWord(prefetch_.low)
+
+	// Raises the exception with integer vector x — x is the vector identifier,
+	// not its address.
+#define RaiseException(x)					\
+	exception_vector_ = x;					\
+	MoveToStateSpecific(StandardException);
+
+	// Copies the current program counter, adjusted to allow for the prefetch queue,
+	// into the instruction_address_ latch, which is the source of the value written
+	// during exceptions.
+#define ReloadInstructionAddress()	\
+	instruction_address_.l = program_counter_.l - 4
+
+	using Mode = InstructionSet::M68k::AddressingMode;
+
+	// Otherwise continue for all time, until back in debt.
+	// Formatting is slightly obtuse here to make this look more like a coroutine.
+	while(true) { switch(state_) {
+
+		// Spin in place, one cycle at a time, until one of DTACK,
+		// BERR or VPA is asserted.
+		BeginState(WaitForDTACK):
+			PerformBusOperation(awaiting_dtack);
+
+			if(dtack_ || berr_ || vpa_) {
+				MoveToStateDynamic(post_dtack_state_);
+			}
+		MoveToStateSpecific(WaitForDTACK);
+
+		// Spin in place until an interrupt arrives.
+		BeginState(STOP):
+			IdleBus(1);
+			captured_interrupt_level_ = bus_interrupt_level_;
+			if(status_.would_accept_interrupt(captured_interrupt_level_)) {
+				MoveToStateSpecific(DoInterrupt);
+			}
+		MoveToStateSpecific(STOP);
+
+		// Perform the RESET exception, which seeds the stack pointer and program
+		// counter, populates the prefetch queue, and then moves to instruction dispatch.
+		BeginState(Reset):
+			IdleBus(7);			// (n-)*5   nn
+
+			// Establish general reset state.
+			status_.begin_exception(7);
+			should_trace_ = 0;
+			did_update_status();
+
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(temporary_address_.l);
+
+			temporary_address_.l = 0;
+			Access(registers_[15].high);	// nF
+
+			temporary_address_.l += 2;
+			Access(registers_[15].low);		// nf
+
+			temporary_address_.l += 2;
+			Access(program_counter_.high);	// nV
+
+			temporary_address_.l += 2;
+			Access(program_counter_.low);	// nv
+
+			Prefetch();			// np
+			IdleBus(1);			// n
+			Prefetch();			// np
+		MoveToStateSpecific(Decode);
+
+		// Perform a 'standard' exception, i.e. a Group 1 or 2.
+		BeginState(StandardException):
+			// Switch to supervisor mode, disable interrupts.
+			captured_status_.w = status_.begin_exception();
+			should_trace_ = 0;
+			did_update_status();
+
+			SetupDataAccess(0, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			// Push status and current program counter.
+			// Write order is wacky here, but I think it's correct.
+			registers_[15].l -= 6;
+			Access(captured_status_);			// ns
+
+			registers_[15].l += 4;
+			Access(instruction_address_.low);	// ns
+
+			registers_[15].l -= 2;
+			Access(instruction_address_.high);	// nS
+
+			registers_[15].l -= 2;
+
+			// Grab new program counter.
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(temporary_address_.l);
+
+			temporary_address_.l = uint32_t(exception_vector_ << 2);
+			Access(program_counter_.high);	// nV
+
+			temporary_address_.l += 2;
+			Access(program_counter_.low);	// nv
+
+			// Populate the prefetch queue.
+			Prefetch();			// np
+			IdleBus(1);			// n
+			Prefetch();			// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(BusOrAddressErrorException):
+			// "The microcode pushes the stack frame in a non consecutive order"
+			// per Ijor's document, but little further information is given.
+			//
+			// So the below is a cross-your-fingers guess based on the constraints
+			// that the information writen, from lowest address to highest is:
+			//
+			// 	R/W, I/N, function code word;		[at -14]
+			//	access address;						[-12]
+			//	instruction register;				[-8]
+			//	status register;					[-6]
+			//	program counter.					[-4]
+			//
+			// With the instruction register definitely being written before the
+			// function code word.
+			//
+			// And the documented bus pattern is:
+			//
+			// nn ns ns nS ns ns ns nS nV nv np  n np
+			//
+			// So, based on the hoopy ordering of a standard exception, maybe:
+			//
+			//	1) program counter low;
+			//	2) captured state;
+			//	3) program counter high;
+			//	4) instruction register;
+			//	5) function code;
+			//	6) access address?
+
+			IdleBus(2);
+
+			// Switch to supervisor mode, disable interrupts.
+			captured_status_.w = status_.begin_exception(7);
+			should_trace_ = 0;
+			did_update_status();
+
+			SetupDataAccess(0, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			// Guess: the written program counter is adjusted to discount the prefetch queue.
+			// COMPLETE GUESS.
+			temporary_address_.l = program_counter_.l - 4;
+			registers_[15].l -= 2;
+			Access(temporary_address_.low);		// ns	[pc.l]
+
+			registers_[15].l -= 4;
+			Access(captured_status_);			// ns	[sr]
+
+			registers_[15].l += 2;
+			Access(temporary_address_.high);	// nS	[pc.h]
+
+			registers_[15].l -= 4;
+			temporary_value_.w = opcode_;
+			Access(temporary_value_.low);		// ns	[instruction register]
+
+			// Construct the function code; which is:
+			//
+			// b4: 1 = was a read; 0 = was a write;
+			// b3: 0 = was reading an instruction; 1 = wasn't;
+			// b2–b0: the regular 68000 function code;
+			// [all other bits]: left over from the instruction register write, above.
+			//
+			// I'm unable to come up with a reason why the function code isn't duplicative
+			// of b3, but given the repetition of supervisor state which is also in the
+			// captured status register I guess maybe it is just duplicative.
+			temporary_value_.w =
+				(temporary_value_.w & ~31) |
+				((bus_error_.operation & Microcycle::Read) ? 0x10 : 0x00) |
+				((bus_error_.operation & Microcycle::IsProgram) ? 0x08 : 0x00) |
+				((bus_error_.operation & Microcycle::IsProgram) ? 0x02 : 0x01) |
+				((captured_status_.w & InstructionSet::M68k::ConditionCode::Supervisor) ? 0x04 : 0x00);
+
+			registers_[15].l -= 6;
+			Access(temporary_value_.low);		// ns	[function code]
+
+			temporary_address_.l = *bus_error_.address;
+			registers_[15].l += 4;
+			Access(temporary_address_.low);		// ns	[error address.l]
+
+			registers_[15].l -= 2;
+			Access(temporary_address_.high);	// nS	[error address.h]
+			registers_[15].l -= 2;
+
+			// Grab new program counter.
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(temporary_address_.l);
+
+			temporary_address_.l = uint32_t(exception_vector_ << 2);
+			Access(program_counter_.high);	// nV
+
+			temporary_address_.l += 2;
+			Access(program_counter_.low);	// nv
+
+			// Populate the prefetch queue.
+			Prefetch();			// np
+			IdleBus(1);			// n
+			Prefetch();			// np
+		MoveToStateSpecific(Decode);
+
+		// Acknowledge an interrupt, thereby obtaining an exception vector,
+		// and do the exception.
+		BeginState(DoInterrupt):
+			IdleBus(3);			// n nn
+
+			// Capture status and switch to supervisor mode.
+			captured_status_.w = status_.begin_exception(captured_interrupt_level_);
+			should_trace_ = 0;
+			did_update_status();
+
+			// Prepare for stack activity.
+			SetupDataAccess(0, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			// Push low part of program counter.
+			registers_[15].l -= 2;
+			Access(instruction_address_.low);	// ns
+
+			// Do the interrupt cycle, to obtain a vector.
+			temporary_address_.l = 0xffff'fff1 | uint32_t(captured_interrupt_level_ << 1);
+			SetupDataAccess(0, Microcycle::InterruptAcknowledge);
+			SetDataAddress(temporary_address_.l);
+			Access(temporary_value_.low);		// ni
+
+			// If VPA is set, autovector.
+			if(vpa_) {
+				temporary_value_.w = uint16_t(InstructionSet::M68k::Exception::InterruptAutovectorBase - 1 + captured_interrupt_level_);
+			}
+
+			// TODO: if bus error is set, treat interrupt as spurious.
+
+			IdleBus(3);							// n- n
+
+			// Do the rest of the stack work.
+			SetupDataAccess(0, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			registers_[15].l -= 4;
+			Access(captured_status_);			// ns
+
+			registers_[15].l += 2;
+			Access(instruction_address_.high);	// nS
+			registers_[15].l -= 2;
+
+			// Grab new program counter.
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(temporary_address_.l);
+
+			temporary_address_.l = uint32_t(temporary_value_.w << 2);
+			Access(program_counter_.high);		// nV
+
+			temporary_address_.l += 2;
+			Access(program_counter_.low);		// nv
+
+			// Populate the prefetch queue.
+			Prefetch();			// np
+			IdleBus(1);			// n
+			Prefetch();			// np
+		MoveToStateSpecific(Decode);
+
+		// Inspect the prefetch queue in order to decode the next instruction,
+		// and segue into the fetching of operands.
+		BeginState(Decode):
+			CheckOverrun();
+
+			// Capture the address of the next instruction.
+			ReloadInstructionAddress();
+
+			// Head off into an interrupt if one is found.
+			if(status_.would_accept_interrupt(captured_interrupt_level_)) {
+				MoveToStateSpecific(DoInterrupt);
+			}
+
+			// Potentially perform a trace.
+			if(should_trace_) {
+				RaiseException(InstructionSet::M68k::Exception::Trace);
+			}
+
+			// Capture the current trace flag.
+			should_trace_ = status_.trace_flag;
+
+			// Read and decode an opcode.
+			opcode_ = prefetch_.high.w;
+			instruction_ = decoder_.decode(opcode_);
+
+			// Signal the bus handler if requested.
+			if constexpr (signal_will_perform) {
+				// Set the state to Decode, so that if the callee pulls any shenanigans in order
+				// to force an exit here, the interpreter can resume without skipping a beat.
+				//
+				// signal_will_perform is overtly a debugging/testing feature.
+				state_ = Decode;
+				bus_handler_.will_perform(instruction_address_.l, opcode_);
+			}
+
+			// Ensure the first parameter is next fetched.
+			next_operand_ = 0;
+
+			/// If operation x requires supervisor privileges, checks whether the user is currently in supervisor mode;
+			/// if not then raises a privilege violation exception.
+#define CheckSupervisor(x)																													\
+		if constexpr (InstructionSet::M68k::requires_supervisor<InstructionSet::M68k::Model::M68000>(InstructionSet::M68k::Operation::x)) {	\
+			if(!status_.is_supervisor) {																									\
+				RaiseException(InstructionSet::M68k::Exception::PrivilegeViolation);														\
+			}																																\
+		}
+
+#define CASE(x)									\
+	case InstructionSet::M68k::Operation::x:	\
+		CheckSupervisor(x);						\
+		operand_flags_ = InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>();
+
+#define StdCASE(x, y)	\
+	CASE(x)	\
+		y;	\
+		\
+		if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::LongWord) {	\
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);	\
+			MoveToStateSpecific(FetchOperand_l);	\
+		} else {	\
+			if constexpr (InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == InstructionSet::M68k::DataSize::Byte) {	\
+				SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);	\
+			} else {	\
+				SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);	\
+			}	\
+			MoveToStateSpecific(FetchOperand_bw);	\
+		}
+
+#define Duplicate(x, y)	\
+	case InstructionSet::M68k::Operation::x:	\
+		static_assert(	\
+			InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::x>() ==		\
+			InstructionSet::M68k::operand_flags<InstructionSet::M68k::Model::M68000, InstructionSet::M68k::Operation::y>() &&		\
+			InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::x>() == 											\
+			InstructionSet::M68k::operand_size<InstructionSet::M68k::Operation::y>() &&												\
+			InstructionSet::M68k::requires_supervisor<InstructionSet::M68k::Model::M68000>(InstructionSet::M68k::Operation::x) == 	\
+			InstructionSet::M68k::requires_supervisor<InstructionSet::M68k::Model::M68000>(InstructionSet::M68k::Operation::y)		\
+		);																															\
+		[[fallthrough]];
+
+#define SpecialCASE(x)	case InstructionSet::M68k::Operation::x: CheckSupervisor(x); MoveToStateSpecific(x)
+
+			switch(instruction_.operation) {
+				case InstructionSet::M68k::Operation::Undefined:
+					if(instruction_.operation == InstructionSet::M68k::Operation::Undefined) {
+						switch(opcode_ & 0xf000) {
+							default:
+								exception_vector_ = InstructionSet::M68k::Exception::IllegalInstruction;
+							break;
+							case 0xa000:
+								exception_vector_ = InstructionSet::M68k::Exception::Line1010;
+							break;
+							case 0xf000:
+								exception_vector_ = InstructionSet::M68k::Exception::Line1111;
+							break;
+						}
+						MoveToStateSpecific(StandardException);
+					}
+
+				StdCASE(NBCD, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np_n;
+					} else {
+						perform_state_ = Perform_np;
+					}
+				})
+
+				Duplicate(CLRb, NEGXb)	Duplicate(NEGb, NEGXb)	Duplicate(NOTb, NEGXb)
+				StdCASE(NEGXb, 		perform_state_ = Perform_np);
+
+				Duplicate(CLRw, NEGXw)	Duplicate(NEGw, NEGXw)	Duplicate(NOTw, NEGXw)
+				StdCASE(NEGXw, 		perform_state_ = Perform_np);
+
+				Duplicate(CLRl, NEGXl)	Duplicate(NEGl, NEGXl)	Duplicate(NOTl, NEGXl)
+				StdCASE(NEGXl,
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np_n;
+					} else {
+						perform_state_ = Perform_np;
+					}
+				);
+
+				StdCASE(SWAP, 		perform_state_ = Perform_np);
+				StdCASE(EXG, 		perform_state_ = Perform_np_n);
+
+				StdCASE(EXTbtow, 	perform_state_ = Perform_np);
+				StdCASE(EXTwtol, 	perform_state_ = Perform_np);
+
+				StdCASE(MOVEb,		perform_state_ = MOVE);
+				Duplicate(MOVEAw, MOVEw)
+				StdCASE(MOVEw,		perform_state_ = MOVE);
+				Duplicate(MOVEAl, MOVEl)
+				StdCASE(MOVEl,		perform_state_ = MOVE);
+
+				StdCASE(CMPb,		perform_state_ = Perform_np);
+				StdCASE(CMPw,		perform_state_ = Perform_np);
+				StdCASE(CMPl,
+					perform_state_ = instruction_.mode(1) == Mode::DataRegisterDirect ? Perform_np_n : Perform_np
+				);
+
+				StdCASE(CMPAw,		perform_state_ = Perform_np_n);
+				StdCASE(CMPAl,		perform_state_ = Perform_np_n);
+
+				Duplicate(ANDb, ORb)	StdCASE(ORb,		perform_state_ = Perform_np);
+				Duplicate(ANDw, ORw)	StdCASE(ORw,		perform_state_ = Perform_np);
+				Duplicate(ANDl, ORl)	StdCASE(ORl, {
+					if(instruction_.mode(1) == Mode::DataRegisterDirect) {
+						switch(instruction_.mode(0)) {
+							default:
+								perform_state_ = Perform_np_n;
+							break;
+							case Mode::DataRegisterDirect:
+							case Mode::ImmediateData:
+								perform_state_ = Perform_np_nn;
+							break;
+						}
+					} else {
+						perform_state_ = Perform_np;
+					}
+				});
+
+				StdCASE(EORb,		perform_state_ = Perform_np);
+				StdCASE(EORw,		perform_state_ = Perform_np);
+				StdCASE(EORl, {
+					if(instruction_.mode(1) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np_nn;
+					} else {
+						perform_state_ = Perform_np;
+					}
+				})
+
+				Duplicate(SBCD, ABCD)
+				CASE(ABCD)
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np_n;
+						SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
+						MoveToStateSpecific(FetchOperand_bw);
+					} else {
+						select_flag_ = Microcycle::SelectByte;
+						MoveToStateSpecific(TwoOp_Predec_bw);
+					}
+
+				StdCASE(CHK,		perform_state_ = CHK);
+
+				Duplicate(SUBb, ADDb)	StdCASE(ADDb,		perform_state_ = Perform_np)
+				Duplicate(SUBw, ADDw)	StdCASE(ADDw,		perform_state_ = Perform_np)
+				Duplicate(SUBl, ADDl)	StdCASE(ADDl, {
+					if(instruction_.mode(0) == Mode::Quick) {
+						perform_state_ = (
+							instruction_.mode(1) == Mode::AddressRegisterDirect ||
+							instruction_.mode(1) == Mode::DataRegisterDirect
+						) ? Perform_np_nn : Perform_np;
+					} else {
+						if(instruction_.mode(1) != Mode::DataRegisterDirect) {
+							perform_state_ = Perform_np;
+						} else {
+							switch(instruction_.mode(0)) {
+								default:
+									perform_state_ = Perform_np_n;
+								break;
+								case Mode::DataRegisterDirect:
+								case Mode::AddressRegisterDirect:
+								case Mode::ImmediateData:
+									perform_state_ = Perform_np_nn;
+								break;
+							}
+						}
+					}
+				})
+
+				Duplicate(SUBAw, ADDAw)	StdCASE(ADDAw, perform_state_ = Perform_np_nn)
+				Duplicate(SUBAl, ADDAl)	StdCASE(ADDAl, {
+					switch(instruction_.mode(0)) {
+						default:
+							perform_state_ = Perform_np_n;
+						break;
+						case Mode::DataRegisterDirect:
+						case Mode::AddressRegisterDirect:
+						case Mode::ImmediateData:
+							perform_state_ = Perform_np_nn;
+						break;
+					}
+				})
+
+				Duplicate(SUBXb, ADDXb)	StdCASE(ADDXb, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np;
+					} else {
+						select_flag_ = Microcycle::SelectByte;
+						MoveToStateSpecific(TwoOp_Predec_bw);
+					}
+				})
+				Duplicate(SUBXw, ADDXw)	StdCASE(ADDXw, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np;
+					} else {
+						select_flag_ = Microcycle::SelectWord;
+						MoveToStateSpecific(TwoOp_Predec_bw);
+					}
+				})
+				Duplicate(SUBXl, ADDXl)	StdCASE(ADDXl, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np_nn;
+					} else {
+						MoveToStateSpecific(TwoOp_Predec_l);
+					}
+				})
+
+				StdCASE(Scc, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Scc_Dn;
+					} else {
+						perform_state_ = Perform_np;
+					}
+				});
+
+				SpecialCASE(DBcc);
+
+				SpecialCASE(Bccb);
+				SpecialCASE(Bccw);
+
+				SpecialCASE(BSRb);
+				SpecialCASE(BSRw);
+
+				Duplicate(JMP, JSR)
+				StdCASE(JSR, {
+					post_ea_state_ =
+						(instruction_.operation == InstructionSet::M68k::Operation::JSR) ?
+							JSR : JMP;
+
+					switch(instruction_.mode(0)) {
+						case Mode::AddressRegisterIndirect:
+							MoveToStateSpecific(JSRJMPAddressRegisterIndirect);
+						case Mode::AddressRegisterIndirectWithDisplacement:
+							MoveToStateSpecific(JSRJMPAddressRegisterIndirectWithDisplacement);
+						case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
+							MoveToStateSpecific(JSRJMPAddressRegisterIndirectWithIndex8bitDisplacement);
+						case Mode::ProgramCounterIndirectWithDisplacement:
+							MoveToStateSpecific(JSRJMPProgramCounterIndirectWithDisplacement);
+						case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
+							MoveToStateSpecific(JSRJMPProgramCounterIndirectWithIndex8bitDisplacement);
+						case Mode::AbsoluteShort:
+							MoveToStateSpecific(JSRJMPAbsoluteShort);
+						case Mode::AbsoluteLong:
+							MoveToStateSpecific(JSRJMPAbsoluteLong);
+
+						default: assert(false);
+					}
+				});
+
+				StdCASE(BTST, {
+					switch(instruction_.mode(1)) {
+						default:
+							perform_state_ = Perform_np;
+						break;
+						case Mode::DataRegisterDirect:
+						case Mode::ImmediateData:
+							perform_state_ = Perform_np_n;
+						break;
+					}
+				});
+
+				Duplicate(BCHG, BSET)
+				StdCASE(BSET, {
+					switch(instruction_.mode(1)) {
+						default:
+							perform_state_ = Perform_np;
+						break;
+						case Mode::DataRegisterDirect:
+						case Mode::ImmediateData:
+							perform_state_ = BCHG_BSET_Dn;
+						break;
+					}
+				});
+
+				StdCASE(BCLR, {
+					switch(instruction_.mode(1)) {
+						default:
+							perform_state_ = Perform_np;
+						break;
+						case Mode::DataRegisterDirect:
+						case Mode::ImmediateData:
+							perform_state_ = BCLR_Dn;
+						break;
+					}
+				});
+
+				StdCASE(MOVEPl, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						MoveToStateSpecific(MOVEPtoM_l);
+					} else {
+						MoveToStateSpecific(MOVEPtoR_l);
+					}
+				});
+
+				StdCASE(MOVEPw, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						MoveToStateSpecific(MOVEPtoM_w);
+					} else {
+						MoveToStateSpecific(MOVEPtoR_w);
+					}
+				});
+
+				Duplicate(ORItoCCR, EORItoCCR);	Duplicate(ANDItoCCR, EORItoCCR);
+				StdCASE(EORItoCCR, 	perform_state_ = LogicalToSR);
+
+				Duplicate(ORItoSR, EORItoSR);	Duplicate(ANDItoSR, EORItoSR);
+				StdCASE(EORItoSR, 	perform_state_ = LogicalToSR);
+
+				StdCASE(MOVEMtoRl,	perform_state_ = MOVEMtoR);
+				StdCASE(MOVEMtoRw,	perform_state_ = MOVEMtoR);
+				StdCASE(MOVEMtoMl,	perform_state_ = MOVEMtoM);
+				StdCASE(MOVEMtoMw,	perform_state_ = MOVEMtoM);
+
+				StdCASE(TSTb,		perform_state_ = Perform_np);
+				StdCASE(TSTw,		perform_state_ = Perform_np);
+				StdCASE(TSTl,		perform_state_ = Perform_np);
+
+				StdCASE(DIVU,		perform_state_ = DIVU_DIVS);
+				StdCASE(DIVS,		perform_state_ = DIVU_DIVS);
+				StdCASE(MULU,		perform_state_ = Perform_idle_dyamic_Dn);
+				StdCASE(MULS,		perform_state_ = Perform_idle_dyamic_Dn);
+
+				StdCASE(LEA, {
+					post_ea_state_ = LEA;
+					MoveToStateSpecific(CalcEffectiveAddressIdleFor8bitDisplacement);
+				});
+				StdCASE(PEA, {
+					post_ea_state_ = PEA;
+					MoveToStateSpecific(CalcEffectiveAddressIdleFor8bitDisplacement);
+				});
+
+				StdCASE(TAS, {
+					// TAS uses a special atomic bus cycle for memory accesses,
+					// but is also available as DataRegisterDirect, with no
+					// memory access whatsoever. So segue elsewhere here only
+					// for the other cases.
+					if(instruction_.mode(0) != Mode::DataRegisterDirect) {
+						post_ea_state_ = TAS;
+						MoveToStateSpecific(CalcEffectiveAddressIdleFor8bitDisplacement);
+					}
+
+					perform_state_ = Perform_np;
+				});
+
+				StdCASE(MOVEtoCCR, 	perform_state_ = MOVEtoCCRSR);
+				StdCASE(MOVEtoSR, 	perform_state_ = MOVEtoCCRSR);
+				StdCASE(MOVEfromSR, {
+					if(instruction_.mode(0) == Mode::DataRegisterDirect) {
+						perform_state_ = Perform_np_n;
+					} else {
+						perform_state_ = Perform_np;
+					}
+				});
+
+				SpecialCASE(RTR);
+				SpecialCASE(RTE);
+				SpecialCASE(RTS);
+
+#define ShiftGroup(suffix, state)								\
+				Duplicate(ASL##suffix, ASR##suffix);			\
+				Duplicate(LSL##suffix, ASR##suffix);			\
+				Duplicate(LSR##suffix, ASR##suffix);			\
+				Duplicate(ROL##suffix, ASR##suffix);			\
+				Duplicate(ROR##suffix, ASR##suffix);			\
+				Duplicate(ROXL##suffix, ASR##suffix);			\
+				Duplicate(ROXR##suffix, ASR##suffix);			\
+				StdCASE(ASR##suffix, perform_state_ = state );
+
+				ShiftGroup(m, Perform_np)
+				ShiftGroup(b, Perform_idle_dyamic_Dn)
+				ShiftGroup(w, Perform_idle_dyamic_Dn)
+				ShiftGroup(l, Perform_idle_dyamic_Dn)
+#undef ShiftGroup
+
+				SpecialCASE(LINKw);
+				SpecialCASE(UNLINK);
+
+				SpecialCASE(RESET);
+				SpecialCASE(NOP);
+
+				StdCASE(MOVEtoUSP, perform_state_ = Perform_np);
+				StdCASE(MOVEfromUSP, perform_state_ = Perform_np);
+
+				SpecialCASE(STOP);
+
+				SpecialCASE(TRAP);
+				SpecialCASE(TRAPV);
+
+				default:
+					assert(false);
+			}
+
+#undef Duplicate
+#undef StdCASE
+#undef CASE
+#undef SpecialCASE
+#undef CheckSupervisor
+
+	// MARK: - Fetch, dispatch.
+
+#define MoveToNextOperand(x)				\
+	++next_operand_;						\
+	if(next_operand_ == 2) {				\
+		MoveToStateDynamic(perform_state_);	\
+	}										\
+	MoveToStateSpecific(x)
+
+		// Check the operand flags to determine whether the byte or word
+		// operand at index next_operand_ needs to be fetched, and if so
+		// then calculate the EA and do so.
+		BeginState(FetchOperand_bw):
+			// Check that this operand is meant to be fetched; if not then either:
+			//
+			//	(i) this operand isn't used; or
+			//	(ii) its address calculation will end up conflated with performance,
+			//		so there's no generic bus-accurate approach.
+			if(!(operand_flags_ & (1 << next_operand_))) {
+				MoveToStateDynamic(perform_state_);
+			}
+
+			// Figure out how to fetch it.
+			switch(instruction_.mode(next_operand_)) {
+				case Mode::AddressRegisterDirect:
+				case Mode::DataRegisterDirect:
+					operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
+				MoveToNextOperand(FetchOperand_bw);
+
+				case Mode::Quick:
+					operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
+				MoveToNextOperand(FetchOperand_bw);
+
+				case Mode::AddressRegisterIndirect:
+					MoveToStateSpecific(FetchAddressRegisterIndirect_bw);
+				case Mode::AddressRegisterIndirectWithPostincrement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithPostincrement_bw);
+				case Mode::AddressRegisterIndirectWithPredecrement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithPredecrement_bw);
+				case Mode::AddressRegisterIndirectWithDisplacement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithDisplacement_bw);
+				case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw);
+				case Mode::ProgramCounterIndirectWithDisplacement:
+					MoveToStateSpecific(FetchProgramCounterIndirectWithDisplacement_bw);
+				case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
+					MoveToStateSpecific(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw);
+				case Mode::AbsoluteShort:
+					MoveToStateSpecific(FetchAbsoluteShort_bw);
+				case Mode::AbsoluteLong:
+					MoveToStateSpecific(FetchAbsoluteLong_bw);
+				case Mode::ImmediateData:
+					MoveToStateSpecific(FetchImmediateData_bw);
+
+				// Should be impossible to reach.
+				default:
+					assert(false);
+			}
+		break;
+
+		// As above, but for .l.
+		BeginState(FetchOperand_l):
+			if(!(operand_flags_ & (1 << next_operand_))) {
+				MoveToStateDynamic(perform_state_);
+			}
+
+			switch(instruction_.mode(next_operand_)) {
+				case Mode::AddressRegisterDirect:
+				case Mode::DataRegisterDirect:
+					operand_[next_operand_] = registers_[instruction_.lreg(next_operand_)];
+				MoveToNextOperand(FetchOperand_l);
+
+				case Mode::Quick:
+					operand_[next_operand_].l = InstructionSet::M68k::quick(opcode_, instruction_.operation);
+				MoveToNextOperand(FetchOperand_l);
+
+				case Mode::AddressRegisterIndirect:
+					MoveToStateSpecific(FetchAddressRegisterIndirect_l);
+				case Mode::AddressRegisterIndirectWithPostincrement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithPostincrement_l);
+				case Mode::AddressRegisterIndirectWithPredecrement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithPredecrement_l);
+				case Mode::AddressRegisterIndirectWithDisplacement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithDisplacement_l);
+				case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
+					MoveToStateSpecific(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l);
+				case Mode::ProgramCounterIndirectWithDisplacement:
+					MoveToStateSpecific(FetchProgramCounterIndirectWithDisplacement_l);
+				case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
+					MoveToStateSpecific(FetchProgramCounterIndirectWithIndex8bitDisplacement_l);
+				case Mode::AbsoluteShort:
+					MoveToStateSpecific(FetchAbsoluteShort_l);
+				case Mode::AbsoluteLong:
+					MoveToStateSpecific(FetchAbsoluteLong_l);
+				case Mode::ImmediateData:
+					MoveToStateSpecific(FetchImmediateData_l);
+
+				// Should be impossible to reach.
+				default:
+					assert(false);
+			}
+		break;
+
+		BeginState(CalcEffectiveAddressIdleFor8bitDisplacement):
+			if(
+				instruction_.mode(next_operand_) != Mode::AddressRegisterIndirectWithIndex8bitDisplacement &&
+				instruction_.mode(next_operand_) != Mode::ProgramCounterIndirectWithIndex8bitDisplacement
+			) {
+				MoveToStateSpecific(CalcEffectiveAddress);
+			}
+
+			IdleBus(1);
+			[[fallthrough]];
+
+		BeginState(CalcEffectiveAddress):
+			switch(instruction_.mode(next_operand_)) {
+				default:
+					MoveToStateDynamic(post_ea_state_);
+
+				case Mode::AddressRegisterIndirect:
+					MoveToStateSpecific(CalcAddressRegisterIndirect);
+				case Mode::AddressRegisterIndirectWithPostincrement:
+					MoveToStateSpecific(CalcAddressRegisterIndirectWithPostincrement);
+				case Mode::AddressRegisterIndirectWithPredecrement:
+					MoveToStateSpecific(CalcAddressRegisterIndirectWithPredecrement);
+				case Mode::AddressRegisterIndirectWithDisplacement:
+					MoveToStateSpecific(CalcAddressRegisterIndirectWithDisplacement);
+				case Mode::AddressRegisterIndirectWithIndex8bitDisplacement:
+					MoveToStateSpecific(CalcAddressRegisterIndirectWithIndex8bitDisplacement);
+				case Mode::ProgramCounterIndirectWithDisplacement:
+					MoveToStateSpecific(CalcProgramCounterIndirectWithDisplacement);
+				case Mode::ProgramCounterIndirectWithIndex8bitDisplacement:
+					MoveToStateSpecific(CalcProgramCounterIndirectWithIndex8bitDisplacement);
+				case Mode::AbsoluteShort:
+					MoveToStateSpecific(CalcAbsoluteShort);
+				case Mode::AbsoluteLong:
+					MoveToStateSpecific(CalcAbsoluteLong);
+			}
+
+	// MARK: - Fetch, addressing modes.
+
+		//
+		// AddressRegisterIndirect
+		//
+		BeginState(FetchAddressRegisterIndirect_bw):
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchAddressRegisterIndirect_l):
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Access(operand_[next_operand_].high);	// nR
+
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcAddressRegisterIndirect):
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+		MoveToStateDynamic(post_ea_state_);
+
+		BeginState(JSRJMPAddressRegisterIndirect):
+			effective_address_[0].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			temporary_address_.l = instruction_address_.l + 2;
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// AddressRegisterIndirectWithPostincrement
+		//
+		BeginState(FetchAddressRegisterIndirectWithPostincrement_bw):
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			registers_[8 + instruction_.reg(next_operand_)].l +=
+				address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
+
+			SetDataAddress(effective_address_[next_operand_].l);
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchAddressRegisterIndirectWithPostincrement_l):
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			registers_[8 + instruction_.reg(next_operand_)].l += 4;
+
+			SetDataAddress(effective_address_[next_operand_].l);
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcAddressRegisterIndirectWithPostincrement):
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			registers_[8 + instruction_.reg(next_operand_)].l +=
+				address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// AddressRegisterIndirectWithPredecrement
+		//
+		BeginState(FetchAddressRegisterIndirectWithPredecrement_bw):
+			registers_[8 + instruction_.reg(next_operand_)].l -=
+				address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			IdleBus(1);								// n
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchAddressRegisterIndirectWithPredecrement_l):
+			registers_[8 + instruction_.reg(next_operand_)].l -= 4;
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			IdleBus(1);								// n
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcAddressRegisterIndirectWithPredecrement):
+			registers_[8 + instruction_.reg(next_operand_)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(next_operand_)];
+			effective_address_[next_operand_].l = registers_[8 + instruction_.reg(next_operand_)].l;
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// AddressRegisterIndirectWithDisplacement
+		//
+		BeginState(FetchAddressRegisterIndirectWithDisplacement_bw):
+			effective_address_[next_operand_].l =
+				registers_[8 + instruction_.reg(next_operand_)].l +
+				uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchAddressRegisterIndirectWithDisplacement_l):
+			effective_address_[next_operand_].l =
+				registers_[8 + instruction_.reg(next_operand_)].l +
+				uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcAddressRegisterIndirectWithDisplacement):
+			effective_address_[next_operand_].l =
+				registers_[8 + instruction_.reg(next_operand_)].l +
+				uint32_t(int16_t(prefetch_.w));
+			Prefetch();								// np
+		MoveToStateDynamic(post_ea_state_);
+
+		BeginState(JSRJMPAddressRegisterIndirectWithDisplacement):
+			effective_address_[0].l =
+				registers_[8 + instruction_.reg(next_operand_)].l +
+				uint32_t(int16_t(prefetch_.w));
+			IdleBus(1);								// n
+			temporary_address_.l = instruction_address_.l + 4;
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// ProgramCounterIndirectWithDisplacement
+		//
+		BeginState(FetchProgramCounterIndirectWithDisplacement_bw):
+			effective_address_[next_operand_].l =
+				program_counter_.l - 2 +
+				uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchProgramCounterIndirectWithDisplacement_l):
+			effective_address_[next_operand_].l =
+				program_counter_.l - 2 +
+				uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcProgramCounterIndirectWithDisplacement):
+			effective_address_[next_operand_].l =
+				program_counter_.l - 2 +
+				uint32_t(int16_t(prefetch_.w));
+			Prefetch();								// np
+		MoveToStateDynamic(post_ea_state_);
+
+		BeginState(JSRJMPProgramCounterIndirectWithDisplacement):
+			effective_address_[0].l =
+				program_counter_.l - 2 +
+				uint32_t(int16_t(prefetch_.w));
+			IdleBus(1);								// n
+			temporary_address_.l = instruction_address_.l + 4;
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// AddressRegisterIndirectWithIndex8bitDisplacement
+		//
+#define d8Xn(base)												\
+	base +														\
+	((prefetch_.w & 0x800) ?									\
+		registers_[prefetch_.w >> 12].l :						\
+		uint32_t(int16_t(registers_[prefetch_.w >> 12].w))) +	\
+	uint32_t(int8_t(prefetch_.b));
+
+		BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_bw):
+			effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			IdleBus(1);								// n
+			Prefetch();								// np
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchAddressRegisterIndirectWithIndex8bitDisplacement_l):
+			effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			IdleBus(1);								// n
+			Prefetch();								// np
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcAddressRegisterIndirectWithIndex8bitDisplacement):
+			effective_address_[next_operand_].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
+			Prefetch();								// np
+			IdleBus(1);								// n
+		MoveToStateDynamic(post_ea_state_);
+
+		BeginState(JSRJMPAddressRegisterIndirectWithIndex8bitDisplacement):
+			effective_address_[0].l = d8Xn(registers_[8 + instruction_.reg(next_operand_)].l);
+			IdleBus(3);								// n nn
+			temporary_address_.l = instruction_address_.l + 4;
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// ProgramCounterIndirectWithIndex8bitDisplacement
+		//
+		BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_bw):
+			effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			IdleBus(1);								// n
+			Prefetch();								// np
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchProgramCounterIndirectWithIndex8bitDisplacement_l):
+			effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			IdleBus(1);								// n
+			Prefetch();								// np
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcProgramCounterIndirectWithIndex8bitDisplacement):
+			effective_address_[next_operand_].l = d8Xn(program_counter_.l - 2);
+			Prefetch();								// np
+			IdleBus(1);								// n
+		MoveToStateDynamic(post_ea_state_);
+
+		BeginState(JSRJMPProgramCounterIndirectWithIndex8bitDisplacement):
+			effective_address_[0].l = d8Xn(program_counter_.l - 2);
+			IdleBus(3);								// n nn
+			temporary_address_.l = instruction_address_.l + 4;
+		MoveToStateDynamic(post_ea_state_);
+
+#undef d8Xn
+
+		//
+		// AbsoluteShort
+		//
+		BeginState(FetchAbsoluteShort_bw):
+			effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchAbsoluteShort_l):
+			effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcAbsoluteShort):
+			effective_address_[next_operand_].l = uint32_t(int16_t(prefetch_.w));
+			Prefetch();								// np
+		MoveToStateDynamic(post_ea_state_);
+
+		BeginState(JSRJMPAbsoluteShort):
+			effective_address_[0].l = uint32_t(int16_t(prefetch_.w));
+			IdleBus(1);								// n
+			temporary_address_.l = instruction_address_.l + 4;
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// AbsoluteLong
+		//
+		BeginState(FetchAbsoluteLong_bw):
+			Prefetch();								// np
+
+			effective_address_[next_operand_].l = prefetch_.l;
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchAbsoluteLong_l):
+			Prefetch();								// np
+
+			effective_address_[next_operand_].l = prefetch_.l;
+			SetDataAddress(effective_address_[next_operand_].l);
+
+			Prefetch();								// np
+			Access(operand_[next_operand_].high);	// nR
+			effective_address_[next_operand_].l += 2;
+			Access(operand_[next_operand_].low);	// nr
+		MoveToNextOperand(FetchOperand_l);
+
+		BeginState(CalcAbsoluteLong):
+			Prefetch();								// np
+			effective_address_[next_operand_].l = prefetch_.l;
+			Prefetch();								// np
+		MoveToStateDynamic(post_ea_state_);
+
+		BeginState(JSRJMPAbsoluteLong):
+			Prefetch();								// np
+			effective_address_[0].l = prefetch_.l;
+			temporary_address_.l = instruction_address_.l + 6;
+		MoveToStateDynamic(post_ea_state_);
+
+		//
+		// ImmediateData
+		//
+		BeginState(FetchImmediateData_bw):
+			operand_[next_operand_].w = prefetch_.w;
+			Prefetch();								// np
+		MoveToNextOperand(FetchOperand_bw);
+
+		BeginState(FetchImmediateData_l):
+			Prefetch();								// np
+			operand_[next_operand_].l = prefetch_.l;
+			Prefetch();								// np
+		MoveToNextOperand(FetchOperand_l);
+
+#undef MoveToNextOperand
+
+	// MARK: - Store.
+
+#define MoveToNextOperand(x)			\
+	++next_operand_;					\
+	if(next_operand_ == 2) {			\
+		MoveToStateSpecific(Decode);	\
+	}									\
+	MoveToStateSpecific(x)
+
+		// Store operand is a lot simpler: only one operand is ever stored, and its address
+		// is already known. So this can either skip straight back to ::Decode if the target
+		// is a register, otherwise a single write operation can occur.
+		BeginState(StoreOperand):
+			switch(instruction_.operand_size()) {
+				case InstructionSet::M68k::DataSize::LongWord:
+					SetupDataAccess(0, Microcycle::SelectWord);
+				MoveToStateSpecific(StoreOperand_l);
+
+				case InstructionSet::M68k::DataSize::Word:
+					SetupDataAccess(0, Microcycle::SelectWord);
+				MoveToStateSpecific(StoreOperand_bw);
+
+				case InstructionSet::M68k::DataSize::Byte:
+					SetupDataAccess(0, Microcycle::SelectByte);
+				MoveToStateSpecific(StoreOperand_bw);
+			}
+
+		BeginState(StoreOperand_bw):
+			if(!(operand_flags_ & 0x4 << next_operand_)) {
+				MoveToNextOperand(StoreOperand_bw);
+			}
+
+			switch(instruction_.mode(next_operand_)) {
+				// Data register: write only the part of the word that has changed.
+				case Mode::DataRegisterDirect: {
+					const uint32_t write_mask = size_masks[int(instruction_.operand_size())];
+					const int reg = instruction_.reg(next_operand_);
+
+					registers_[reg].l =
+						(operand_[next_operand_].l & write_mask) |
+						(registers_[reg].l & ~write_mask);
+				}
+				MoveToNextOperand(StoreOperand_bw);
+
+				// Address register: always rewrite the whole word; the smaller
+				// result will have been sign extended.
+				case Mode::AddressRegisterDirect:
+					registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
+				MoveToNextOperand(StoreOperand_bw);
+
+				default: break;
+			}
+
+			SetDataAddress(effective_address_[next_operand_].l);
+			Access(operand_[next_operand_].low);		// nw
+		MoveToNextOperand(StoreOperand_bw);
+
+		BeginState(StoreOperand_l):
+			if(!(operand_flags_ & 0x4 << next_operand_)) {
+				MoveToNextOperand(StoreOperand_l);
+			}
+
+			if(instruction_.mode(next_operand_) <= Mode::AddressRegisterDirect) {
+				registers_[instruction_.lreg(next_operand_)] = operand_[next_operand_];
+				MoveToNextOperand(StoreOperand_l);
+			}
+
+			SetupDataAccess(0, Microcycle::SelectWord);
+			SetDataAddress(effective_address_[next_operand_].l);
+			Access(operand_[next_operand_].low);		// nw
+
+			effective_address_[next_operand_].l -= 2;
+			Access(operand_[next_operand_].high);		// nW
+		MoveToNextOperand(StoreOperand_l);
+
+#define PerformDynamic()	\
+	InstructionSet::M68k::perform<InstructionSet::M68k::Model::M68000>(	\
+		instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
+
+#define PerformSpecific(x)	\
+	InstructionSet::M68k::perform<	\
+		InstructionSet::M68k::Model::M68000,	\
+		ProcessorBase,	\
+		InstructionSet::M68k::Operation::x	\
+	>(	\
+		instruction_, operand_[0], operand_[1], status_, *static_cast<ProcessorBase *>(this));
+
+		//
+		// Various generic forms of perform.
+		//
+#define MoveToWritePhase()					\
+	if(operand_flags_ & 0x0c) {				\
+		next_operand_ = 0;					\
+		MoveToStateSpecific(StoreOperand);	\
+	} else {								\
+		MoveToStateSpecific(Decode);		\
+	}
+
+		BeginState(Perform_np):
+			PerformDynamic();
+			Prefetch();			// np
+		MoveToWritePhase();
+
+		BeginState(Perform_np_n):
+			PerformDynamic();
+			Prefetch();			// np
+			IdleBus(1);			// n
+		MoveToWritePhase();
+
+		BeginState(Perform_np_nn):
+			PerformDynamic();
+			Prefetch();			// np
+			IdleBus(2);			// nn
+		MoveToWritePhase();
+
+#undef MoveToWritePhase
+
+
+		//
+		// Specific forms of perform...
+		//
+
+		BeginState(MOVE):
+			PerformDynamic();
+
+			// In all cases except predecrement mode: do the usual address
+			// calculate and storage, then do the next prefetch and decode.
+			//
+			// In predecrement mode: do the prefetch, then write the result.
+			//
+			// For here, lump data and address register direct in with predec,
+			// so that all that's left is modes that write to memory and then
+			// prefetch.
+			switch(instruction_.mode(1)) {
+				case Mode::DataRegisterDirect: {
+					const uint32_t write_mask = size_masks[int(instruction_.operand_size())];
+					const int reg = instruction_.reg(1);
+
+					registers_[reg].l =
+						(operand_[1].l & write_mask) |
+						(registers_[reg].l & ~write_mask);
+				}
+				MoveToStateSpecific(MOVE_prefetch_decode);
+
+				case Mode::AddressRegisterDirect:
+					registers_[8 + instruction_.reg(1)].l = operand_[1].l;
+				MoveToStateSpecific(MOVE_prefetch_decode);
+
+				case Mode::AddressRegisterIndirectWithPredecrement:
+				MoveToStateSpecific(MOVE_predec);
+
+				default: break;
+			}
+
+			next_operand_ = 1;
+			post_ea_state_ = MOVE_complete;
+		MoveToStateSpecific(CalcEffectiveAddress);
+
+		BeginState(MOVE_prefetch_decode):
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(MOVE_predec):
+			Prefetch();
+
+			SetDataAddress(registers_[8 + instruction_.reg(1)].l);
+			switch(instruction_.operand_size()) {
+				case InstructionSet::M68k::DataSize::LongWord:
+				MoveToStateSpecific(MOVE_predec_l);
+
+				case InstructionSet::M68k::DataSize::Word:
+					SetupDataAccess(0, Microcycle::SelectWord);
+					registers_[8 + instruction_.reg(1)].l -= 2;
+				break;
+
+				case InstructionSet::M68k::DataSize::Byte:
+					SetupDataAccess(0, Microcycle::SelectByte);
+					registers_[8 + instruction_.reg(1)].l -=
+						address_increments[0][instruction_.reg(next_operand_)];
+				break;
+			}
+
+			SetDataAddress(registers_[8 + instruction_.reg(1)].l);
+			Access(operand_[1].low);
+		MoveToStateSpecific(Decode);
+
+		BeginState(MOVE_predec_l):
+			SetupDataAccess(0, Microcycle::SelectWord);
+
+			registers_[8 + instruction_.reg(1)].l -= 2;
+			Access(operand_[1].low);
+			registers_[8 + instruction_.reg(1)].l -= 2;
+			Access(operand_[1].high);
+		MoveToStateSpecific(Decode);
+
+		BeginState(MOVE_complete):
+			SetDataAddress(effective_address_[1].l);
+
+			switch(instruction_.operand_size()) {
+				case InstructionSet::M68k::DataSize::LongWord:
+					SetupDataAccess(0, Microcycle::SelectWord);
+				MoveToStateSpecific(MOVE_complete_l);
+
+				case InstructionSet::M68k::DataSize::Word:
+					SetupDataAccess(0, Microcycle::SelectWord);
+				break;
+
+				case InstructionSet::M68k::DataSize::Byte:
+					SetupDataAccess(0, Microcycle::SelectByte);
+				break;
+			}
+
+			Access(operand_[1].low);
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(MOVE_complete_l):
+			Access(operand_[1].high);
+			effective_address_[1].l += 2;
+			Access(operand_[1].low);
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// [ABCD/SBCD/SUBX/ADDX] (An)-, (An)-
+		//
+		BeginState(TwoOp_Predec_bw):
+			IdleBus(1);					// n
+
+			SetupDataAccess(Microcycle::Read, select_flag_);
+
+			SetDataAddress(registers_[8 + instruction_.reg(0)].l);
+			registers_[8 + instruction_.reg(0)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(0)];
+			Access(operand_[0].low);	// nr
+
+			SetDataAddress(registers_[8 + instruction_.reg(1)].l);
+			registers_[8 + instruction_.reg(1)].l -= address_increments[int(instruction_.operand_size())][instruction_.reg(1)];
+			Access(operand_[1].low);	// nr
+
+			Prefetch();					// np
+
+			PerformDynamic();
+
+			SetupDataAccess(0, select_flag_);
+			Access(operand_[1].low);	// nw
+		MoveToStateSpecific(Decode);
+
+		BeginState(TwoOp_Predec_l):
+			IdleBus(1);					// n
+
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+
+			SetDataAddress(registers_[8 + instruction_.reg(0)].l);
+			registers_[8 + instruction_.reg(0)].l -= 2;
+			Access(operand_[0].low);	// nr
+
+			registers_[8 + instruction_.reg(0)].l -= 2;
+			Access(operand_[0].high);	// nR
+
+			SetDataAddress(registers_[8 + instruction_.reg(1)].l);
+			registers_[8 + instruction_.reg(1)].l -= 2;
+			Access(operand_[1].low);	// nr
+
+			registers_[8 + instruction_.reg(1)].l -= 2;
+			Access(operand_[1].high);	// nR
+
+			PerformDynamic();
+
+			SetupDataAccess(0, Microcycle::SelectWord);
+
+			registers_[8 + instruction_.reg(1)].l += 2;
+			Access(operand_[1].low);	// nw
+
+			Prefetch();					// np
+
+			registers_[8 + instruction_.reg(1)].l -= 2;
+			Access(operand_[1].high);	// nW
+		MoveToStateSpecific(Decode);
+
+		//
+		// CHK
+		//
+		BeginState(CHK):
+			Prefetch();			// np
+			PerformSpecific(CHK);
+
+			// Proper next state will have been set by the flow controller
+			// call-in; just allow dispatch to whatever it was.
+		break;
+
+		BeginState(CHK_no_trap):
+			IdleBus(3);			// nn n
+		MoveToStateSpecific(Decode);
+
+		BeginState(CHK_was_over):
+			IdleBus(2);			// nn
+			ReloadInstructionAddress();
+		RaiseException(InstructionSet::M68k::Exception::CHK);
+
+		BeginState(CHK_was_under):
+			IdleBus(3);			// n nn
+			ReloadInstructionAddress();
+		RaiseException(InstructionSet::M68k::Exception::CHK);
+
+		//
+		// Scc
+		//
+		BeginState(Scc_Dn):
+			Prefetch();			// np
+			PerformSpecific(Scc);
+
+			// Next state will be set by did_scc.
+		break;
+
+		BeginState(Scc_Dn_did_set):
+			IdleBus(1);			// n
+			[[fallthrough]];
+		BeginState(Scc_Dn_did_not_set):
+			next_operand_ = 0;
+		MoveToStateSpecific(StoreOperand);
+
+		//
+		// DBcc
+		//
+		BeginState(DBcc):
+			operand_[0] = registers_[instruction_.reg(0)];
+			operand_[1].w = uint16_t(int16_t(prefetch_.w));
+			PerformSpecific(DBcc);
+			registers_[instruction_.reg(0)].w = operand_[0].w;
+
+			// Next state was set by complete_dbcc.
+		break;
+
+		BeginState(DBcc_branch_taken):
+			IdleBus(1);		// n
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(DBcc_condition_true):
+			IdleBus(2);		// n n
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(DBcc_counter_overflow):
+			IdleBus(1);		// n
+
+			// Yacht lists an extra np here; I'm assuming it's a read from where
+			// the PC would have gone, had the branch been taken. So do that,
+			// but then reset the PC to where it would have been.
+			Prefetch();		// np
+
+			program_counter_.l = instruction_address_.l + 4;
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		//
+		// Bcc [.b and .w]
+		//
+		BeginState(Bccb):
+			operand_[0].b = uint8_t(opcode_);
+			PerformSpecific(Bccb);
+
+			// Next state was set by complete_bcc.
+		break;
+
+		BeginState(Bccw):
+			operand_[0].w = prefetch_.w;
+			PerformSpecific(Bccw);
+
+			// Next state was set by complete_bcc.
+		break;
+
+		BeginState(Bcc_branch_taken):
+			IdleBus(1);		// n
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(Bccb_branch_not_taken):
+			IdleBus(2);		// nn
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(Bccw_branch_not_taken):
+			IdleBus(2);		// nn
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+
+#define Push(x)									\
+	SetupDataAccess(0, Microcycle::SelectWord);	\
+	SetDataAddress(registers_[15].l);			\
+	registers_[15].l -= 4;						\
+	Access(x.high);								\
+	registers_[15].l += 2;						\
+	Access(x.low);								\
+	registers_[15].l -= 2;
+
+#define Pop(x)													\
+	SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);	\
+	SetDataAddress(registers_[15].l);							\
+	Access(x.high);												\
+	registers_[15].l += 2;										\
+	Access(x.low);												\
+	registers_[15].l += 2;
+
+		//
+		// BSR
+		//
+		BeginState(BSRb):
+		BeginState(BSRw):
+			IdleBus(1);		// n
+
+			// Calculate the address of the next instruction and the next program counter.
+			if(instruction_.operand_size() == InstructionSet::M68k::DataSize::Word) {
+				temporary_address_.l = instruction_address_.l + 4;
+				program_counter_.l = instruction_address_.l + uint32_t(int16_t(prefetch_.w)) + 2;
+			} else {
+				temporary_address_.l = instruction_address_.l + 2;
+				program_counter_.l = instruction_address_.l + uint32_t(int8_t(opcode_)) + 2;
+			}
+
+			// Push the next instruction address to the stack.
+			Push(temporary_address_);
+
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		//
+		// JSR [push only; address calculation elsewhere], JMP
+		//
+		BeginState(JSR):
+			// Update the program counter and prefetch once.
+			program_counter_.l = effective_address_[0].l;
+			Prefetch();		// np
+
+			// Push the old PC onto the stack in upper, lower order.
+			Push(temporary_address_);
+
+			// Prefetch once more.
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(JMP):
+			// Update the program counter and prefetch once.
+			program_counter_.l = effective_address_[0].l;
+			Prefetch();		// np
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		//
+		// BSET, BCHG, BCLR
+		//
+		BeginState(BCHG_BSET_Dn):
+			PerformDynamic();
+
+			Prefetch();
+			IdleBus(1 + dynamic_instruction_length_);
+			registers_[instruction_.reg(1)] = operand_[1];
+		MoveToStateSpecific(Decode);
+
+		BeginState(BCLR_Dn):
+			PerformSpecific(BCLR);
+
+			Prefetch();
+			IdleBus(2 + dynamic_instruction_length_);
+			registers_[instruction_.reg(1)] = operand_[1];
+		MoveToStateSpecific(Decode);
+
+		//
+		// MOVEP
+		//
+		BeginState(MOVEPtoM_l):
+			temporary_address_.l = registers_[8 + instruction_.reg(1)].l + uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(temporary_address_.l);
+			SetupDataAccess(0, Microcycle::SelectByte);
+
+			Prefetch();						// np
+
+			temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 24);
+			Access(temporary_value_.low);	// nW
+
+			temporary_address_.l += 2;
+			temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 16);
+			Access(temporary_value_.low);	// nW
+
+			temporary_address_.l += 2;
+			temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 8);
+			Access(temporary_value_.low);	// nw
+
+			temporary_address_.l += 2;
+			temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l);
+			Access(temporary_value_.low);	// nw
+
+			Prefetch();						// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(MOVEPtoM_w):
+			temporary_address_.l = registers_[8 + instruction_.reg(1)].l + uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(temporary_address_.l);
+			SetupDataAccess(0, Microcycle::SelectByte);
+
+			Prefetch();						// np
+
+			temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l >> 8);
+			Access(temporary_value_.low);	// nW
+
+			temporary_address_.l += 2;
+			temporary_value_.b = uint8_t(registers_[instruction_.reg(0)].l);
+			Access(temporary_value_.low);	// nw
+
+			Prefetch();						// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(MOVEPtoR_l):
+			temporary_address_.l = registers_[8 + instruction_.reg(0)].l + uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(temporary_address_.l);
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
+
+			Prefetch();						// np
+
+			Access(temporary_value_.low);	// nR
+			registers_[instruction_.reg(1)].l = uint32_t(temporary_value_.b << 24);
+
+			temporary_address_.l += 2;
+			Access(temporary_value_.low);	// nR
+			registers_[instruction_.reg(1)].l |= uint32_t(temporary_value_.b << 16);
+
+			temporary_address_.l += 2;
+			Access(temporary_value_.low);	// nr
+			registers_[instruction_.reg(1)].l |= uint32_t(temporary_value_.b << 8);
+
+			temporary_address_.l += 2;
+			Access(temporary_value_.low);	// nr
+			registers_[instruction_.reg(1)].l |= uint32_t(temporary_value_.b);
+
+			Prefetch();						// np
+		MoveToStateSpecific(Decode);
+
+		BeginState(MOVEPtoR_w):
+			temporary_address_.l = registers_[8 + instruction_.reg(0)].l + uint32_t(int16_t(prefetch_.w));
+			SetDataAddress(temporary_address_.l);
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectByte);
+
+			Prefetch();						// np
+
+			Access(temporary_value_.low);	// nR
+			registers_[instruction_.reg(1)].w = uint16_t(temporary_value_.b << 8);
+
+			temporary_address_.l += 2;
+			Access(temporary_value_.low);	// nr
+			registers_[instruction_.reg(1)].w |= uint16_t(temporary_value_.b);
+
+			Prefetch();						// np
+		MoveToStateSpecific(Decode);
+
+		//
+		// [EORI/ORI/ANDI] #, [CCR/SR]
+		//
+		BeginState(LogicalToSR):
+			IdleBus(4);
+
+			// Perform the operation.
+			PerformDynamic();
+
+			// Recede the program counter and prefetch twice.
+			program_counter_.l -= 2;
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// MOVEM M --> R
+		//
+		BeginState(MOVEMtoR):
+			post_ea_state_ =
+				(instruction_.operation == InstructionSet::M68k::Operation::MOVEMtoRl) ?
+					MOVEMtoR_l_read : MOVEMtoR_w_read;
+			next_operand_ = 1;
+			register_index_ = 0;
+
+			SetDataAddress(effective_address_[1].l);
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+		MoveToStateSpecific(CalcEffectiveAddress);
+
+		BeginState(MOVEMtoR_w_read):
+			// If there's nothing left to read, move on.
+			if(!operand_[0].w) {
+				MoveToStateSpecific(MOVEMtoR_finish);
+			}
+
+			// Find the next register to read, read it and sign extend it.
+			while(!(operand_[0].w & 1)) {
+				operand_[0].w >>= 1;
+				++register_index_;
+			}
+			Access(registers_[register_index_].low);
+			registers_[register_index_].l = uint32_t(int16_t(registers_[register_index_].w));
+			effective_address_[1].l += 2;
+
+			// Drop the bottom bit.
+			operand_[0].w >>= 1;
+			++register_index_;
+		MoveToStateSpecific(MOVEMtoR_w_read);
+
+		BeginState(MOVEMtoR_l_read):
+			// If there's nothing left to read, move on.
+			if(!operand_[0].w) {
+				MoveToStateSpecific(MOVEMtoR_finish);
+			}
+
+			// Find the next register to read, read it.
+			while(!(operand_[0].w & 1)) {
+				operand_[0].w >>= 1;
+				++register_index_;
+			}
+			Access(registers_[register_index_].high);
+			effective_address_[1].l += 2;
+			Access(registers_[register_index_].low);
+			effective_address_[1].l += 2;
+
+			// Drop the bottom bit.
+			operand_[0].w >>= 1;
+			++register_index_;
+		MoveToStateSpecific(MOVEMtoR_l_read);
+
+		BeginState(MOVEMtoR_finish):
+			// Perform one more read, spuriously.
+			Access(temporary_value_.low);	// nr
+
+			// Write the address back to the register if
+			// this was postincrement mode.
+			if(instruction_.mode(1) == Mode::AddressRegisterIndirectWithPostincrement) {
+				registers_[8 + instruction_.reg(1)].l = effective_address_[1].l;
+			}
+
+			Prefetch();	// np
+		MoveToStateSpecific(Decode);
+
+		//
+		// MOVEM R --> M
+		//
+		BeginState(MOVEMtoM):
+			next_operand_ = 1;
+			SetDataAddress(effective_address_[1].l);
+			SetupDataAccess(0, Microcycle::SelectWord);
+
+			// Predecrement writes registers the other way around, but still reads the
+			// mask from LSB.
+			if(instruction_.mode(1) == Mode::AddressRegisterIndirectWithPredecrement) {
+				register_index_ = 15;
+				effective_address_[1].l = registers_[8 + instruction_.reg(1)].l;
+
+				// Don't go through the usual calculate EA path because: (i) the test above
+				// has already told us the addressing mode, and it's trivial; and (ii) the
+				// predecrement isn't actually wanted.
+				if(instruction_.operation == InstructionSet::M68k::Operation::MOVEMtoMl) {
+					MoveToStateSpecific(MOVEMtoM_l_write_predec);
+				} else {
+					MoveToStateSpecific(MOVEMtoM_w_write_predec);
+				}
+			}
+
+			register_index_ = 0;
+			post_ea_state_ =
+				(instruction_.operation == InstructionSet::M68k::Operation::MOVEMtoMl) ?
+					MOVEMtoM_l_write : MOVEMtoM_w_write;
+		MoveToStateSpecific(CalcEffectiveAddress);
+
+		BeginState(MOVEMtoM_w_write):
+			// If there's nothing left to read, move on.
+			if(!operand_[0].w) {
+				MoveToStateSpecific(MOVEMtoM_finish);
+			}
+
+			// Find the next register to write, write it.
+			while(!(operand_[0].w & 1)) {
+				operand_[0].w >>= 1;
+				++register_index_;
+			}
+			Access(registers_[register_index_].low);
+			effective_address_[1].l += 2;
+
+			// Drop the bottom bit.
+			operand_[0].w >>= 1;
+			++register_index_;
+		MoveToStateSpecific(MOVEMtoM_w_write);
+
+		BeginState(MOVEMtoM_l_write):
+			// If there's nothing left to read, move on.
+			if(!operand_[0].w) {
+				MoveToStateSpecific(MOVEMtoM_finish);
+			}
+
+			// Find the next register to write, write it.
+			while(!(operand_[0].w & 1)) {
+				operand_[0].w >>= 1;
+				++register_index_;
+			}
+
+			Access(registers_[register_index_].high);
+			effective_address_[1].l += 2;
+			Access(registers_[register_index_].low);
+			effective_address_[1].l += 2;
+
+			// Drop the bottom bit.
+			operand_[0].w >>= 1;
+			++register_index_;
+		MoveToStateSpecific(MOVEMtoM_l_write);
+
+		BeginState(MOVEMtoM_w_write_predec):
+			// If there's nothing left to read, move on.
+			if(!operand_[0].w) {
+				MoveToStateSpecific(MOVEMtoM_finish);
+			}
+
+			// Find the next register to write, write it.
+			while(!(operand_[0].w & 1)) {
+				operand_[0].w >>= 1;
+				--register_index_;
+			}
+			effective_address_[1].l -= 2;
+			Access(registers_[register_index_].low);
+
+			// Drop the bottom bit.
+			operand_[0].w >>= 1;
+			--register_index_;
+		MoveToStateSpecific(MOVEMtoM_w_write_predec);
+
+		BeginState(MOVEMtoM_l_write_predec):
+			// If there's nothing left to read, move on.
+			if(!operand_[0].w) {
+				MoveToStateSpecific(MOVEMtoM_finish);
+			}
+
+			// Find the next register to write, write it.
+			while(!(operand_[0].w & 1)) {
+				operand_[0].w >>= 1;
+				--register_index_;
+			}
+
+			effective_address_[1].l -= 2;
+			Access(registers_[register_index_].low);
+			effective_address_[1].l -= 2;
+			Access(registers_[register_index_].high);
+
+			// Drop the bottom bit.
+			operand_[0].w >>= 1;
+			--register_index_;
+		MoveToStateSpecific(MOVEMtoM_l_write_predec);
+
+		BeginState(MOVEMtoM_finish):
+			// Write the address back to the register if
+			// this was predecrement mode.
+			if(instruction_.mode(1) == Mode::AddressRegisterIndirectWithPredecrement) {
+				registers_[8 + instruction_.reg(1)].l = effective_address_[1].l;
+			}
+
+			Prefetch();	// np
+		MoveToStateSpecific(Decode);
+
+		//
+		// DIVU and DIVUS
+		//
+		BeginState(DIVU_DIVS):
+			// Set a no-interrupt-occurred sentinel.
+			exception_vector_ = -1;
+
+			// Perform the instruction.
+			PerformDynamic();
+
+			// Delay the correct amount of time.
+			IdleBus(dynamic_instruction_length_);
+
+			// Either dispatch an exception or don't.
+			if(exception_vector_ >= 0) {
+				MoveToStateSpecific(StandardException);
+			}
+
+			// DIVU and DIVS are always to a register, so just write back here
+			// to save on dispatch costs.
+			registers_[instruction_.reg(1)] = operand_[1];
+
+			Prefetch();		// np
+		MoveToStateSpecific(Decode);
+
+		//
+		// MULU, MULS and shifts
+		//
+		BeginState(Perform_idle_dyamic_Dn):
+			Prefetch();		// np
+
+			// Perform the instruction.
+			PerformDynamic();
+
+			// Delay the correct amount of time.
+			IdleBus(dynamic_instruction_length_);
+
+			// MULU and MULS are always to a register, so just write back here
+			// to save on dispatch costs.
+			registers_[instruction_.reg(1)] = operand_[1];
+
+		MoveToStateSpecific(Decode);
+
+		//
+		// LEA
+		//
+		BeginState(LEA):
+			registers_[8 + instruction_.reg(1)].l = effective_address_[0].l;
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// PEA
+		//
+		BeginState(PEA):
+			Push(effective_address_[0]);
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// TAS
+		//
+		BeginState(TAS):
+			// Populate all addresses.
+			tas_cycles[0].address = tas_cycles[1].address =
+			tas_cycles[2].address =
+			tas_cycles[3].address = tas_cycles[4].address = &effective_address_[0].l;
+
+			// Populate values to the relevant subset.
+			tas_cycles[0].value = tas_cycles[1].value =
+			tas_cycles[3].value = tas_cycles[4].value = &operand_[0].low;
+
+			// First two parts: the read.
+			PerformBusOperation(tas_cycles[0]);
+			CompleteAccess(tas_cycles[1]);
+
+			// Third part: processing time.
+			PerformBusOperation(tas_cycles[2]);
+
+			// Do the actual TAS operation.
+			status_.overflow_flag = status_.carry_flag = 0;
+			status_.zero_result = operand_[0].b;
+			status_.negative_flag = operand_[0].b & 0x80;
+
+			// Final parts: write back.
+			operand_[0].b |= 0x80;
+			PerformBusOperation(tas_cycles[3]);
+			CompleteAccess(tas_cycles[4]);
+
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// MOVE to [CCR/SR]
+		//
+		BeginState(MOVEtoCCRSR):
+			PerformDynamic();
+
+			// Rewind the program counter and prefetch twice.
+			IdleBus(2);
+			program_counter_.l -= 2;
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// RTR, RTS, RTE
+		//
+		BeginState(RTS):
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			Access(program_counter_.high);
+			registers_[15].l += 2;
+			Access(program_counter_.low);
+			registers_[15].l += 2;
+
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(RTE):
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			registers_[15].l += 2;
+			Access(program_counter_.high);
+			registers_[15].l += 2;
+			Access(program_counter_.low);
+
+			registers_[15].l -= 4;
+			Access(temporary_value_.low);
+			registers_[15].l += 6;
+			status_.set_status(temporary_value_.w);
+
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(RTR):
+			SetupDataAccess(Microcycle::Read, Microcycle::SelectWord);
+			SetDataAddress(registers_[15].l);
+
+			registers_[15].l += 2;
+			Access(program_counter_.high);
+			registers_[15].l += 2;
+			Access(program_counter_.low);
+
+			registers_[15].l -= 4;
+			Access(temporary_value_.low);
+			registers_[15].l += 6;
+			status_.set_ccr(temporary_value_.w);
+
+			Prefetch();
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// LINK[.w] and UNLINK
+		//
+		BeginState(LINKw):
+			Prefetch();
+
+			// Ensure that the stack pointer is [seemingly] captured after
+			// having been decremented by four, if it's what should be captured.
+			registers_[15].l -= 4;
+			temporary_address_ = registers_[8 + instruction_.reg(0)];
+			registers_[15].l += 4;
+
+			// Push will actually decrement the stack pointer.
+			Push(temporary_address_);
+
+			// Make the exchange.
+			registers_[8 + instruction_.reg(0)].l = registers_[15].l;
+			registers_[15].l += uint32_t(int16_t(prefetch_.high.w));
+
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		BeginState(UNLINK):
+			registers_[15] = registers_[8 + instruction_.reg(0)];
+			Pop(temporary_address_);
+			registers_[8 + instruction_.reg(0)] = temporary_address_;
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// RESET
+		//
+		BeginState(RESET):
+			IdleBus(2);
+			PerformBusOperation(reset_cycle);
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// NOP
+		//
+		BeginState(NOP):
+			Prefetch();
+		MoveToStateSpecific(Decode);
+
+		//
+		// TRAP, TRAPV
+		//
+
+		// TODO: which program counter is appropriate for TRAP? That of the TRAP,
+		// or that of the instruction after?
+		BeginState(TRAP):
+			IdleBus(2);
+			instruction_address_.l += 2;	// Push the address of the instruction after the trap.
+		RaiseException((opcode_ & 15) + InstructionSet::M68k::Exception::TrapBase);
+
+		BeginState(TRAPV):
+			Prefetch();
+			if(!status_.overflow_flag) {
+				MoveToStateSpecific(Decode);
+			}
+			instruction_address_.l += 2;	// Push the address of the instruction after the trap.
+		RaiseException(InstructionSet::M68k::Exception::TRAPV);
+
+		default:
+			printf("Unhandled state: %d; opcode is %04x\n", state_, opcode_);
+			assert(false);
+	}}
+
+#undef Pop
+#undef Push
+#undef PerformDynamic
+#undef PerformSpecific
+#undef RaiseException
+#undef Prefetch
+#undef ReadProgramWord
+#undef ReadDataWord
+#undef AccessPair
+#undef CompleteAccess
+#undef WaitForDTACK
+#undef IdleBus
+#undef PerformBusOperation
+#undef MoveToStateSpecific
+#undef MoveToStateDynamic
+#undef CheckOverrun
+#undef Spend
+#undef ConsiderExit
+#undef ReloadInstructionAddress
+
+}
+
+// MARK: - Flow Controller.
+
+void ProcessorBase::did_update_status() {
+	// Shuffle the stack pointers.
+	stack_pointers_[is_supervisor_] = registers_[15];
+	registers_[15] = stack_pointers_[int(status_.is_supervisor)];
+	is_supervisor_ = int(status_.is_supervisor);
+}
+
+void ProcessorBase::did_chk(bool was_under, bool was_over) {
+	if(was_over) {
+		state_ = CHK_was_over;
+	} else if(was_under) {
+		state_ = CHK_was_under;
+	} else {
+		state_ = CHK_no_trap;
+	}
+}
+
+void ProcessorBase::did_scc(bool did_set_ff) {
+	state_ = did_set_ff ? Scc_Dn_did_set : Scc_Dn_did_not_set;
+}
+
+void ProcessorBase::complete_dbcc(bool matched_condition, bool overflowed, int16_t offset) {
+	// The actual DBcc rule is: branch if !matched_condition and !overflowed; but I think
+	// that a spurious read from the intended destination PC occurs if overflowed, so update
+	// the PC for any case of !matched_condition and rely on the DBcc_counter_overflow to
+	// set it back.
+	if(!matched_condition) {
+		state_ = overflowed ? DBcc_counter_overflow : DBcc_branch_taken;
+		program_counter_.l = instruction_address_.l + uint32_t(offset) + 2;
+		return;
+	}
+	state_ = DBcc_condition_true;
+}
+
+template <typename IntT> void ProcessorBase::complete_bcc(bool take_branch, IntT offset) {
+	if(take_branch) {
+		program_counter_.l = instruction_address_.l + uint32_t(offset) + 2;
+		state_ = Bcc_branch_taken;
+		return;
+	}
+
+	state_ =
+		(instruction_.operation == InstructionSet::M68k::Operation::Bccb) ?
+			Bccb_branch_not_taken : Bccw_branch_not_taken;
+}
+
+void ProcessorBase::did_bit_op(int bit_position) {
+	dynamic_instruction_length_ = int(bit_position > 15);
+}
+
+template <bool did_overflow> void ProcessorBase::did_divu(uint32_t dividend, uint32_t divisor) {
+	if(!divisor) {
+		dynamic_instruction_length_ = 4;	// nn nn precedes the usual exception activity.
+		return;
+	}
+
+	if(did_overflow) {
+		dynamic_instruction_length_ = 3;	// Covers the nn n to get into the loop.
+		return;
+	}
+
+	// Calculate cost; this is based on the flowchart in yacht.txt.
+	// I could actually calculate the division result using this code,
+	// since this is a classic divide algorithm, but would rather that
+	// errors produce incorrect timing only, not incorrect timing plus
+	// incorrect results.
+	dynamic_instruction_length_ =
+		3 +		// nn n to get into the loop;
+		30 +	// nn per iteration of the loop below;
+		3;		// n nn upon completion of the loop.
+
+	divisor <<= 16;
+	for(int c = 0; c < 15; ++c) {
+		if(dividend & 0x8000'0000) {
+			dividend = (dividend << 1) - divisor;
+		} else {
+			dividend <<= 1;
+
+			// Yacht.txt, and indeed a real microprogram, would just subtract here
+			// and test the sign of the result, but this is easier to follow:
+			if (dividend >= divisor) {
+				dividend -= divisor;
+				dynamic_instruction_length_ += 1;	// i.e. the original nn plus one further n before going down the MSB=0 route.
+			} else {
+				dynamic_instruction_length_ += 2;	// The costliest path (since in real life it's a subtraction and then a step
+				// back from there) — all costs accrue. So the fixed nn loop plus another n,
+				// plus another one.
+			}
+		}
+	}
+}
+
+#define convert_to_bit_count_16(x)			\
+	x = ((x & 0xaaaa) >> 1) + (x & 0x5555);	\
+	x = ((x & 0xcccc) >> 2) + (x & 0x3333);	\
+	x = ((x & 0xf0f0) >> 4) + (x & 0x0f0f);	\
+	x = ((x & 0xff00) >> 8) + (x & 0x00ff);
+
+template <bool did_overflow> void ProcessorBase::did_divs(int32_t dividend, int32_t divisor) {
+	// The route to spotting divide by 0 is just nn nn.
+	if(!divisor) {
+		dynamic_instruction_length_ = 4;	// nn nn precedes the usual exception activity.
+		return;
+	}
+
+	// It's either six or seven microcycles to get into the main loop, depending
+	// on dividend sign.
+	dynamic_instruction_length_ = 6 + (dividend < 0);
+
+	if(did_overflow) {
+		return;
+	}
+
+	// There's a fixed cost per bit, plus an additional one for each that is zero.
+	//
+	// The sign bit does not count here; it's the high fifteen bits that matter
+	// only, in the unsigned version of the result.
+	//
+	// Disclaimer: per the flowchart it looks to me like this constant should be 60
+	// rather than 49 — four microcycles per bit. But the number 49 makes this
+	// algorithm exactly fit the stated minimum and maximum costs. Possibly the
+	// undefined difference between a nop cycle an an idle wait is relevant here?
+	dynamic_instruction_length_ += 49;
+
+	int result_bits = ~abs(dividend / divisor) & 0xfffe;
+	convert_to_bit_count_16(result_bits);
+	dynamic_instruction_length_ += result_bits;
+
+	// Determine the tail cost; a divisor of less than 0 leads to one exit,
+	// a divisor of greater than zero makes the result a function of the
+	// sign of the dividend.
+	//
+	// In all cases, this is counting from 'No more bits' in the Yacht diagram.
+	if(divisor < 0) {
+		dynamic_instruction_length_ += 4;
+		return;
+	}
+
+	if(dividend < 0) {
+		dynamic_instruction_length_ += 5;
+	} else {
+		dynamic_instruction_length_ += 3;
+	}
+}
+
+template <typename IntT> void ProcessorBase::did_mulu(IntT multiplier) {
+	// Count number of bits set.
+	convert_to_bit_count_16(multiplier);
+	dynamic_instruction_length_ = 17 + multiplier;
+}
+
+template <typename IntT> void ProcessorBase::did_muls(IntT multiplier) {
+	// Count number of transitions from 0 to 1 or from 1 to 0 — i.e. the
+	// number of times that a bit is not equal to the one to its right.
+	// Treat the bit to the right of b0 as 0.
+	int number_of_pairs = (multiplier ^ (multiplier << 1)) & 0xffff;
+	convert_to_bit_count_16(number_of_pairs);
+	dynamic_instruction_length_ = 17 + number_of_pairs;
+}
+
+#undef convert_to_bit_count_16
+
+template <typename IntT> void ProcessorBase::did_shift(int bits_shifted) {
+	if constexpr (sizeof(IntT) == 4) {
+		dynamic_instruction_length_ = bits_shifted + 2;
+	} else {
+		dynamic_instruction_length_ = bits_shifted + 1;
+	}
+}
+
+template <bool use_current_instruction_pc> void ProcessorBase::raise_exception(int vector) {
+	// No overt action is taken here; instructions that might throw an exception are required
+	// to check-in after the fact.
+	//
+	// As implemented above, that means:
+	//
+	//	* DIVU;
+	//	* DIVS.
+	exception_vector_ = vector;
+}
+
+inline void ProcessorBase::tas(Preinstruction instruction, uint32_t) {
+	// This will be reached only if addressing mode is Dn.
+	const uint8_t value = registers_[instruction.reg(0)].b;
+	registers_[instruction.reg(0)].b |= 0x80;
+
+	status_.overflow_flag = status_.carry_flag = 0;
+	status_.zero_result = value;
+	status_.negative_flag = value & 0x80;
+}
+
+inline void ProcessorBase::move_to_usp(uint32_t address) {
+	stack_pointers_[0].l = address;
+}
+
+inline void ProcessorBase::move_from_usp(uint32_t &address) {
+	address = stack_pointers_[0].l;
+}
+
+// MARK: - External state.
+
+template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
+CPU::MC68000Mk2::State Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::get_state() {
+	CPU::MC68000Mk2::State state;
+
+	// This isn't true, but will ensure that both stack_pointers_ have their proper values.
+	did_update_status();
+
+	for(int c = 0; c < 7; c++) {
+		state.registers.data[c] = registers_[c].l;
+		state.registers.address[c] = registers_[c + 8].l;
+	}
+	state.registers.data[7] = registers_[7].l;
+
+	state.registers.program_counter = program_counter_.l;
+	state.registers.status = status_.status();
+	state.registers.user_stack_pointer = stack_pointers_[0].l;
+	state.registers.supervisor_stack_pointer = stack_pointers_[1].l;
+
+	return state;
+}
+
+template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
+void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::set_state(const CPU::MC68000Mk2::State &state) {
+	// Copy registers and the program counter.
+	for(int c = 0; c < 7; c++) {
+		registers_[c].l = state.registers.data[c];
+		registers_[c + 8].l = state.registers.address[c];
+	}
+	registers_[7].l = state.registers.data[7];
+	program_counter_.l = state.registers.program_counter;
+
+	// Set status first in order to get the proper is-supervisor flag in place.
+	status_.set_status(state.registers.status);
+
+	// Update stack pointers, being careful to copy the right one.
+	stack_pointers_[0].l = state.registers.user_stack_pointer;
+	stack_pointers_[1].l = state.registers.supervisor_stack_pointer;
+	registers_[15] = stack_pointers_[is_supervisor_];
+
+	// Ensure the local is-supervisor flag is updated.
+	did_update_status();
+}
+
+template <class BusHandler, bool dtack_is_implicit, bool permit_overrun, bool signal_will_perform>
+void Processor<BusHandler, dtack_is_implicit, permit_overrun, signal_will_perform>::decode_from_state(const InstructionSet::M68k::RegisterSet &registers) {
+	// Populate registers.
+	CPU::MC68000Mk2::State state;
+	state.registers = registers;
+	set_state(state);
+
+	// Ensure the state machine will resume at decode.
+	state_ = Decode;
+
+	// Fill the prefetch queue.
+	captured_interrupt_level_ = bus_interrupt_level_;
+
+	read_program.value = &prefetch_.high;
+	bus_handler_.perform_bus_operation(read_program_announce, is_supervisor_);
+	bus_handler_.perform_bus_operation(read_program, is_supervisor_);
+	program_counter_.l += 2;
+
+	read_program.value = &prefetch_.low;
+	bus_handler_.perform_bus_operation(read_program_announce, is_supervisor_);
+	bus_handler_.perform_bus_operation(read_program, is_supervisor_);
+	program_counter_.l += 2;
+}
+
+}
+}
+
+#endif /* _8000Mk2Implementation_h */
diff --git a/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
new file mode 100644
index 000000000..358dceb2c
--- /dev/null
+++ b/Processors/68000Mk2/Implementation/68000Mk2Storage.hpp
@@ -0,0 +1,220 @@
+//
+//  68000Mk2Storage.hpp
+//  Clock Signal
+//
+//  Created by Thomas Harte on 16/05/2022.
+//  Copyright © 2022 Thomas Harte. All rights reserved.
+//
+
+#ifndef _8000Mk2Storage_h
+#define _8000Mk2Storage_h
+
+#include "../../../InstructionSets/M68k/Decoder.hpp"
+#include "../../../InstructionSets/M68k/Perform.hpp"
+#include "../../../InstructionSets/M68k/Status.hpp"
+
+#include <limits>
+
+namespace CPU {
+namespace MC68000Mk2 {
+
+struct ProcessorBase: public InstructionSet::M68k::NullFlowController {
+	ProcessorBase() {
+		read_program_announce.address = read_program.address = &program_counter_.l;
+	}
+
+	int state_ = std::numeric_limits<int>::min();
+
+	/// Counts time left on the clock before the current batch of processing
+	/// is complete; may be less than zero.
+	HalfCycles time_remaining_;
+
+	/// E clock phase.
+	HalfCycles e_clock_phase_;
+
+	/// Current supervisor state, for direct provision to the bus handler.
+	int is_supervisor_ = 1;
+
+	// A decoder for instructions, plus all collected information about the
+	// current instruction.
+	InstructionSet::M68k::Predecoder<InstructionSet::M68k::Model::M68000> decoder_;
+	InstructionSet::M68k::Preinstruction instruction_;
+	uint16_t opcode_;
+	uint8_t operand_flags_;
+	SlicedInt32 instruction_address_;
+
+	// Register state.
+	InstructionSet::M68k::Status status_;
+	SlicedInt32 program_counter_;
+	SlicedInt32 registers_[16]{};		// D0–D7 followed by A0–A7.
+	SlicedInt32 stack_pointers_[2];
+
+	/// Current state of the DTACK input.
+	bool dtack_ = false;
+	/// Current state of the VPA input.
+	bool vpa_ = false;
+	/// Current state of the BERR input.
+	bool berr_ = false;
+	/// Current input interrupt level.
+	int bus_interrupt_level_ = 0;
+
+	// Whether to trace at the end of this instruction.
+	InstructionSet::M68k::Status::FlagT should_trace_ = 0;
+
+	// I don't have great information on the 68000 interrupt latency; as a first
+	// guess, capture the bus interrupt level upon every prefetch, and use that for
+	// the inner-loop decision.
+	int captured_interrupt_level_ = 0;
+
+	/// Contains the prefetch queue; the most-recently fetched thing is the
+	/// low portion of this word, and the thing fetched before that has
+	/// proceeded to the high portion.
+	SlicedInt32 prefetch_;
+
+	// Temporary storage for the current instruction's operands
+	// and the corresponding effective addresses.
+	CPU::SlicedInt32 operand_[2];
+	CPU::SlicedInt32 effective_address_[2];
+
+	/// If currently in the wait-for-DTACK state, this indicates where to go
+	/// upon receipt of DTACK or VPA. BERR will automatically segue
+	/// into the proper exception.
+	int post_dtack_state_ = 0;
+
+	/// If using CalcEffectiveAddress, this is the state to adopt after the
+	/// effective address for next_operand_ has been calculated.
+	int post_ea_state_ = 0;
+
+	/// The perform state for this operation.
+	int perform_state_ = 0;
+
+	/// When fetching or storing operands, this is the next one to fetch
+	/// or store.
+	int next_operand_ = -1;
+
+	/// Storage for a temporary address, which can't be a local because it'll
+	/// be used to populate microcycles, which may persist beyond an entry
+	/// and exit of run_for (especially between an address announcement, and
+	/// a data select).
+	SlicedInt32 temporary_address_;
+
+	/// Storage for a temporary value; primarily used by MOVEP to split a 32-bit
+	/// source into bus-compatible byte units.
+	SlicedInt32 temporary_value_;
+
+	/// A record of the exception to trigger.
+	int exception_vector_ = 0;
+
+	/// Transient storage for exception processing.
+	SlicedInt16 captured_status_;
+
+	/// An internal flag used during various dynamically-sized instructions
+	/// (e.g. BCHG, DIVU) to indicate how much additional processing happened;
+	/// this is measured in microcycles.
+	int dynamic_instruction_length_ = 0;
+
+	/// Two bits of state for MOVEM, being the curent register and what to
+	/// add to it to get to the next register.
+	int register_index_ = 0, register_delta_ = 0;
+
+	// A lookup table that aids with effective address calculation in
+	// predecrement and postincrement modes; index as [size][register]
+	// and note that [0][7] is 2 rather than 1.
+	static constexpr uint32_t address_increments[3][8] = {
+		{ 1, 1, 1, 1, 1, 1, 1, 2, },
+		{ 2, 2, 2, 2, 2, 2, 2, 2, },
+		{ 4, 4, 4, 4, 4, 4, 4, 4, },
+	};
+
+	// A lookup table that ensures write-back to data registers affects
+	// only the correct bits.
+	static constexpr uint32_t size_masks[3] = { 0xff, 0xffff, 0xffff'ffff };
+
+	// Assumptions used by the lookup tables above:
+	static_assert(int(InstructionSet::M68k::DataSize::Byte) == 0);
+	static_assert(int(InstructionSet::M68k::DataSize::Word) == 1);
+	static_assert(int(InstructionSet::M68k::DataSize::LongWord) == 2);
+
+	/// Used by some dedicated read-modify-write perform patterns to
+	/// determine the size of the bus operation.
+	Microcycle::OperationT select_flag_ = 0;
+
+	// Captured bus/address-error state.
+	Microcycle bus_error_;
+
+	// Flow controller methods implemented.
+	using Preinstruction = InstructionSet::M68k::Preinstruction;
+	template <typename IntT> void did_mulu(IntT);
+	template <typename IntT> void did_muls(IntT);
+	inline void did_chk(bool, bool);
+	inline void did_scc(bool);
+	template <typename IntT> void did_shift(int);
+	template <bool did_overflow> void did_divu(uint32_t, uint32_t);
+	template <bool did_overflow> void did_divs(int32_t, int32_t);
+	inline void did_bit_op(int);
+	inline void did_update_status();
+	template <typename IntT> void complete_bcc(bool, IntT);
+	inline void complete_dbcc(bool, bool, int16_t);
+	inline void move_to_usp(uint32_t);
+	inline void move_from_usp(uint32_t &);
+	inline void tas(Preinstruction, uint32_t);
+	template <bool use_current_instruction_pc = true> void raise_exception(int);
+
+	// These aren't implemented because the specific details of the implementation
+	// mean that the performer call-out isn't necessary.
+	template <typename IntT> void movep(Preinstruction, uint32_t, uint32_t) {}
+	template <typename IntT> void movem_toM(Preinstruction, uint32_t, uint32_t) {}
+	template <typename IntT> void movem_toR(Preinstruction, uint32_t, uint32_t) {}
+	void jsr(uint32_t) {}
+	void bsr(uint32_t) {}
+	void jmp(uint32_t) {}
+	inline void pea(uint32_t) {}
+	inline void link(Preinstruction, uint32_t) {}
+	inline void unlink(uint32_t &) {}
+	inline void rtr() {}
+	inline void rte() {}
+	inline void rts() {}
+	inline void reset() {}
+	inline void stop() {}
+
+	// Some microcycles that will be modified as required and used in the main loop;
+	// the semantics of a switch statement make in-place declarations awkward and
+	// some of these may persist across multiple calls to run_for.
+	Microcycle idle{0};
+
+	// Read a program word. All accesses via the program counter are word sized.
+	Microcycle read_program_announce {
+		Microcycle::Read | Microcycle::NewAddress | Microcycle::IsProgram
+	};
+	Microcycle read_program {
+		Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsProgram
+	};
+
+	// Read a data word or byte.
+	Microcycle access_announce {
+		Microcycle::Read | Microcycle::NewAddress | Microcycle::IsData
+	};
+	Microcycle access {
+		Microcycle::Read | Microcycle::SameAddress | Microcycle::SelectWord | Microcycle::IsData
+	};
+
+	// TAS.
+	Microcycle tas_cycles[5] = {
+		{ Microcycle::Read | Microcycle::NewAddress | Microcycle::IsData },
+		{ Microcycle::Read | Microcycle::SameAddress | Microcycle::IsData | Microcycle::SelectByte },
+		{ Microcycle::SameAddress },
+		{ Microcycle::SameAddress | Microcycle::IsData },
+		{ Microcycle::SameAddress | Microcycle::IsData | Microcycle::SelectByte },
+	};
+
+	// Reset.
+	Microcycle reset_cycle { Microcycle::Reset, HalfCycles(248) };
+
+	// Holding spot when awaiting DTACK/etc.
+	Microcycle awaiting_dtack;
+};
+
+}
+}
+
+#endif /* _8000Mk2Storage_h */