From fdef8901abbaab19a3c57f8b789a776b33a4b011 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Fri, 8 Mar 2024 14:13:34 -0500 Subject: [PATCH] Double down on uint32_t. --- InstructionSets/ARM/Executor.hpp | 2 +- InstructionSets/ARM/OperationMapper.hpp | 36 +++++++++---------- InstructionSets/ARM/Registers.hpp | 8 ++--- Machines/Acorn/Archimedes/Archimedes.cpp | 45 +++++++++++++----------- 4 files changed, 48 insertions(+), 43 deletions(-) diff --git a/InstructionSets/ARM/Executor.hpp b/InstructionSets/ARM/Executor.hpp index ac76bc98a..f8571e9b7 100644 --- a/InstructionSets/ARM/Executor.hpp +++ b/InstructionSets/ARM/Executor.hpp @@ -475,7 +475,7 @@ struct Executor { address_error = address >= (1 << 26); // Write out registers 1 to 14. - for(int c = 0; c < 15; c++) { + for(uint32_t c = 0; c < 15; c++) { if(list & (1 << c)) { access(registers_[c]); diff --git a/InstructionSets/ARM/OperationMapper.hpp b/InstructionSets/ARM/OperationMapper.hpp index 01c210d76..1df66b0e1 100644 --- a/InstructionSets/ARM/OperationMapper.hpp +++ b/InstructionSets/ARM/OperationMapper.hpp @@ -43,15 +43,15 @@ struct WithShiftControlBits { constexpr WithShiftControlBits(uint32_t opcode) noexcept : opcode_(opcode) {} /// The operand 2 register index if @c operand2_is_immediate() is @c false; meaningless otherwise. - int operand2() const { return opcode_ & 0xf; } + uint32_t operand2() const { return opcode_ & 0xf; } /// The type of shift to apply to operand 2 if @c operand2_is_immediate() is @c false; meaningless otherwise. ShiftType shift_type() const { return ShiftType((opcode_ >> 5) & 3); } /// @returns @c true if the amount to shift by should be taken from a register; @c false if it is an immediate value. bool shift_count_is_register() const { return opcode_ & (1 << 4); } /// The shift amount register index if @c shift_count_is_register() is @c true; meaningless otherwise. - int shift_register() const { return (opcode_ >> 8) & 0xf; } + uint32_t shift_register() const { return (opcode_ >> 8) & 0xf; } /// The amount to shift by if @c shift_count_is_register() is @c false; meaningless otherwise. - int shift_amount() const { return (opcode_ >> 7) & 0x1f; } + uint32_t shift_amount() const { return (opcode_ >> 7) & 0x1f; } protected: uint32_t opcode_; @@ -160,10 +160,10 @@ struct DataProcessing: public WithShiftControlBits { using WithShiftControlBits::WithShiftControlBits; /// The destination register index. i.e. Rd. - int destination() const { return (opcode_ >> 12) & 0xf; } + uint32_t destination() const { return (opcode_ >> 12) & 0xf; } /// The operand 1 register index. i.e. Rn. - int operand1() const { return (opcode_ >> 16) & 0xf; } + uint32_t operand1() const { return (opcode_ >> 16) & 0xf; } // // Immediate values for operand 2. @@ -246,13 +246,13 @@ struct SingleDataTransfer: public WithShiftControlBits { using WithShiftControlBits::WithShiftControlBits; /// The destination register index. i.e. 'Rd' for LDR. - int destination() const { return (opcode_ >> 12) & 0xf; } + uint32_t destination() const { return (opcode_ >> 12) & 0xf; } /// The destination register index. i.e. 'Rd' for STR. - int source() const { return (opcode_ >> 12) & 0xf; } + uint32_t source() const { return (opcode_ >> 12) & 0xf; } /// The base register index. i.e. 'Rn'. - int base() const { return (opcode_ >> 16) & 0xf; } + uint32_t base() const { return (opcode_ >> 16) & 0xf; } /// The immediate offset, if @c offset_is_register() was @c false; meaningless otherwise. uint32_t immediate() const { return opcode_ & 0xfff; } @@ -307,11 +307,11 @@ private: struct CoprocessorDataOperation { constexpr CoprocessorDataOperation(uint32_t opcode) noexcept : opcode_(opcode) {} - int operand1() const { return (opcode_ >> 16) & 0xf; } - int operand2() const { return opcode_ & 0xf; } - int destination() const { return (opcode_ >> 12) & 0xf; } - int coprocessor() const { return (opcode_ >> 8) & 0xf; } - int information() const { return (opcode_ >> 5) & 0x7; } + uint32_t operand1() const { return (opcode_ >> 16) & 0xf; } + uint32_t operand2() const { return opcode_ & 0xf; } + uint32_t destination() const { return (opcode_ >> 12) & 0xf; } + uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; } + uint32_t information() const { return (opcode_ >> 5) & 0x7; } private: uint32_t opcode_; @@ -340,11 +340,11 @@ private: struct CoprocessorRegisterTransfer { constexpr CoprocessorRegisterTransfer(uint32_t opcode) noexcept : opcode_(opcode) {} - int operand1() const { return (opcode_ >> 16) & 0xf; } - int operand2() const { return opcode_ & 0xf; } - int destination() const { return (opcode_ >> 12) & 0xf; } - int coprocessor() const { return (opcode_ >> 8) & 0xf; } - int information() const { return (opcode_ >> 5) & 0x7; } + uint32_t operand1() const { return (opcode_ >> 16) & 0xf; } + uint32_t operand2() const { return opcode_ & 0xf; } + uint32_t destination() const { return (opcode_ >> 12) & 0xf; } + uint32_t coprocessor() const { return (opcode_ >> 8) & 0xf; } + uint32_t information() const { return (opcode_ >> 5) & 0x7; } private: uint32_t opcode_; diff --git a/InstructionSets/ARM/Registers.hpp b/InstructionSets/ARM/Registers.hpp index 5bc688b57..41cfe429a 100644 --- a/InstructionSets/ARM/Registers.hpp +++ b/InstructionSets/ARM/Registers.hpp @@ -270,12 +270,12 @@ struct Registers { mode_ = target_mode; } - uint32_t &operator[](size_t offset) { - return active_[offset]; + uint32_t &operator[](uint32_t offset) { + return active_[static_cast(offset)]; } - uint32_t operator[](size_t offset) const { - return active_[offset]; + uint32_t operator[](uint32_t offset) const { + return active_[static_cast(offset)]; } private: diff --git a/Machines/Acorn/Archimedes/Archimedes.cpp b/Machines/Acorn/Archimedes/Archimedes.cpp index 90d287c94..c82c9d2ac 100644 --- a/Machines/Acorn/Archimedes/Archimedes.cpp +++ b/Machines/Acorn/Archimedes/Archimedes.cpp @@ -170,6 +170,7 @@ struct Interrupts { bool read(uint32_t address, uint8_t &value) { const auto target = address & 0x7f; + logger.error().append("IO controller read from %08x", address); switch(target) { default: break; @@ -202,12 +203,12 @@ struct Interrupts { return true; } - logger.error().append("TODO: IO controller read from %08x", address); return false; } bool write(uint32_t address, uint8_t value) { const auto target = address & 0x7f; + logger.error().append("IO controller write of %02x at %08x", value, address); switch(target) { default: break; @@ -249,7 +250,6 @@ struct Interrupts { return true; } - logger.error().append("TODO: IO controller write of %02x at %08x", value, address); return false; } @@ -714,32 +714,37 @@ class ConcreteMachine: } // TODO: pipeline prefetch? - static bool log = false; + static bool log = true; - if(executor_.pc() == 0x03801a1c) { - printf(""); - } +// if(executor_.pc() == 0x0380096c) { +// printf(""); +// } // log |= (executor_.pc() > 0 && executor_.pc() < 0x03800000); - log |= (executor_.pc() == 0x038019e0); + log |= executor_.pc() == 0x38008e0; +// log |= (executor_.pc() > 0x03801000); +// log &= (executor_.pc() != 0x038019f8); + + if(executor_.pc() == 0x38008e0) //0x038019f8) + return; if(log) { - logger.info().append("%08x: %08x prior:[r0:%08x r1:%08x r4:%08x r10:%08x r14:%08x]", - executor_.pc(), - instruction, - executor_.registers()[0], - executor_.registers()[1], - executor_.registers()[4], - executor_.registers()[10], - executor_.registers()[14] - ); + auto info = logger.info(); + info.append("%08x: %08x prior:[", executor_.pc(), instruction); + for(size_t c = 0; c < 15; c++) { + info.append("r%d:%08x ", c, executor_.registers()[c]); + } + info.append("]"); } InstructionSet::ARM::execute(instruction, executor_); // if( -// last_link != executor_.registers()[14] || -// last_r0 != executor_.registers()[0] || -// last_r10 != executor_.registers()[10] || -// last_r1 != executor_.registers()[1] +//// executor_.pc() > 0x038021d0 && +// ( +// last_link != executor_.registers()[14] || +// last_r0 != executor_.registers()[0] || +// last_r10 != executor_.registers()[10] || +// last_r1 != executor_.registers()[1] +// ) // ) { // logger.info().append("%08x modified R14 to %08x; R0 to %08x; R10 to %08x; R1 to %08x", // last_pc,