From fe8db1873c8085376eb64ce34fde7b0ccf960d11 Mon Sep 17 00:00:00 2001 From: Thomas Harte Date: Sun, 21 May 2017 20:32:06 -0400 Subject: [PATCH] Added 16-bit ADC and SBC table entries; once again extended logging. --- Processors/Z80/Z80.hpp | 50 +++++++++++++++++++++++++++++++----- Processors/Z80/Z80AllRAM.cpp | 2 +- 2 files changed, 44 insertions(+), 8 deletions(-) diff --git a/Processors/Z80/Z80.hpp b/Processors/Z80/Z80.hpp index 89de3c946..a40724574 100644 --- a/Processors/Z80/Z80.hpp +++ b/Processors/Z80/Z80.hpp @@ -258,20 +258,55 @@ template class Processor: public MicroOpScheduler { NOP_ROW(), /* 0x10 */ NOP_ROW(), /* 0x20 */ NOP_ROW(), /* 0x30 */ - NOP_ROW(), /* 0x40 */ - NOP_ROW(), /* 0x50 */ - NOP_ROW(), /* 0x60 */ + /* 0x40 IN B, (C) */ XX, /* 0x41 OUT (C), B */ XX, + /* 0x42 SBC HL, BC */ Program(WAIT(7), SBC16(hl_, bc_)), + /* 0x43 LD (nn), BC */ XX, + /* 0x44 NEG */ XX, /* 0x45 RETN */ XX, + /* 0x46 IM 0 */ XX, /* 0x47 LD I, A */ XX, + /* 0x48 IN C, (C) */ XX, /* 0x49 OUT (C), C */ XX, + /* 0x4a ADC HL, BC */ Program(WAIT(7), ADC16(hl_, bc_)), + /* 0x4b LD BC, (nn) */ XX, + /* 0x4c NEG */ XX, /* 0x4d RETI */ XX, + /* 0x4e IM 0/1 */ XX, /* 0x4f LD R, A */ XX, + /* 0x50 IN D, (C) */ XX, /* 0x51 OUT (C), D */ XX, + /* 0x52 SBC HL, DE */ Program(WAIT(7), SBC16(hl_, de_)), + /* 0x53 LD (nn), DE */ XX, + /* 0x54 NEG */ XX, /* 0x55 RETN */ XX, + /* 0x56 IM 1 */ XX, /* 0x57 LD A, I */ XX, + /* 0x58 IN E, (C) */ XX, /* 0x59 OUT (C), E */ XX, + /* 0x5a ADC HL, DE */ Program(WAIT(7), ADC16(hl_, de_)), + /* 0x5b LD DE, (nn) */ XX, + /* 0x5c NEG */ XX, /* 0x5d RETN */ XX, + /* 0x5e IM 2 */ XX, /* 0x5f LD A, R */ XX, + /* 0x60 IN H, (C) */ XX, /* 0x61 OUT (C), H */ XX, + /* 0x62 SBC HL, HL */ Program(WAIT(7), SBC16(hl_, hl_)), + /* 0x63 LD (nn), HL */ XX, + /* 0x64 NEG */ XX, /* 0x65 RETN */ XX, + /* 0x66 IM 0 */ XX, /* 0x67 RRD */ XX, + /* 0x68 IN L, (C) */ XX, /* 0x69 OUT (C), L */ XX, + /* 0x6a ADC HL, HL */ Program(WAIT(7), ADC16(hl_, hl_)), + /* 0x6b LD HL, (nn) */ XX, + /* 0x6c NEG */ XX, /* 0x6d RETN */ XX, + /* 0x6e IM 0/1 */ XX, /* 0x6f RLD */ XX, /* 0x70 IN (C) */ XX, /* 0x71 OUT (C), 0 */ XX, - /* 0x72 SBC HL, SP */ XX, /* 0x73 LD (nn), SP */ Program(FETCH16(temp16_, pc_), STORE16L(sp_, temp16_)), + /* 0x72 SBC HL, SP */ Program(WAIT(7), SBC16(hl_, sp_)), + /* 0x73 LD (nn), SP */ Program(FETCH16(temp16_, pc_), STORE16L(sp_, temp16_)), /* 0x74 NEG */ XX, /* 0x75 RETN */ XX, /* 0x76 IM 1 */ XX, /* 0x77 XX */ XX, /* 0x78 IN A, (C) */ XX, /* 0x79 OUT (C), A */ XX, - /* 0x7a ADC HL, SP */ XX, /* 0x7b LD SP, (nn) */ Program(FETCH16(temp16_, pc_), FETCH16L(sp_, temp16_)), + /* 0x7a ADC HL, SP */ Program(WAIT(7), ADC16(hl_, sp_)), + /* 0x7b LD SP, (nn) */ Program(FETCH16(temp16_, pc_), FETCH16L(sp_, temp16_)), /* 0x7c NEG */ XX, /* 0x7d RETN */ XX, - /* 0x7e IM 2 */ XX, /* 0x7f XX */ XX, + /* 0x7e IM 2 */ XX, /* 0x7f XX */ XX, NOP_ROW(), /* 0x80 */ NOP_ROW(), /* 0x90 */ - NOP_ROW(), /* 0xa0 */ + /* 0xa0 LDI */ XX, + /* 0xa1 CPI */ XX, + /* 0xa2 INI */ XX, /* 0xa3 OTI */ XX, + XX, XX, XX, XX, + /* 0xa8 LDD */ XX, /* 0xa9 CPD */ XX, + /* 0xaa IND */ XX, /* 0xab OTD */ XX, + XX, XX, XX, XX, /* 0xb0 LDIR */ Program(FETCHL(temp8_, hl_), STOREL(temp8_, de_), WAIT(2), {MicroOp::LDIR}, WAIT(5)), /* 0xb1 CPIR */ XX, /* 0xb2 INIR */ XX, /* 0xb3 OTIR */ XX, @@ -843,6 +878,7 @@ template class Processor: public MicroOpScheduler { case MicroOp::SetInstructionPage: schedule_program(fetch_decode_execute); current_instruction_page_ = ((InstructionPage *)operation->source)->instructions; + printf("+ "); break; case MicroOp::CalculateIndexAddress: diff --git a/Processors/Z80/Z80AllRAM.cpp b/Processors/Z80/Z80AllRAM.cpp index 53583daef..9c96a5a3f 100644 --- a/Processors/Z80/Z80AllRAM.cpp +++ b/Processors/Z80/Z80AllRAM.cpp @@ -16,7 +16,7 @@ AllRAMProcessor::AllRAMProcessor() : ::CPU::AllRAMProcessor(65536) {} int AllRAMProcessor::perform_machine_cycle(const MachineCycle *cycle) { switch(cycle->operation) { case BusOperation::ReadOpcode: -// printf("! "); + printf("! %02x\n", memory_[*cycle->address]); check_address_for_trap(*cycle->address); case BusOperation::Read: // printf("r %04x [%02x] AF:%04x BC:%04x DE:%04x HL:%04x SP:%04x\n", *cycle->address, memory_[*cycle->address], get_value_of_register(CPU::Z80::Register::AF), get_value_of_register(CPU::Z80::Register::BC), get_value_of_register(CPU::Z80::Register::DE), get_value_of_register(CPU::Z80::Register::HL), get_value_of_register(CPU::Z80::Register::StackPointer));