6502/CLK
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14,854 Commits 5 Branches 152 Tags
SmallCallable
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37 Commits
Author SHA1 Message Date
Thomas Harte 2f68d38879 Rationalise JMP as an LEA. 2026-04-12 08:59:40 -04:00
Thomas Harte 116ed6f497 Correct LEAx length, and hence normalise CD90-640 disk RPM. 2026-04-06 14:32:59 -04:00
Thomas Harte ba042610af Add missing header, adjust LEAx timing. 2026-04-06 12:24:48 -04:00
Thomas Harte 83612bf193 Differentiate "zero-cost" (i.e. no internal cycles) operations. 
64 failures outstanding.
 2026-03-26 09:16:19 -04:00
Thomas Harte 05a85b6ba9 Resolve various compiler warnings: primarily ~'s promotion to int. 2026-03-25 13:57:32 -04:00
Thomas Harte 372893a05a Add support for passive NOP observation. 2026-03-25 09:44:15 -04:00
Thomas Harte b925783251 Round out indexed address calculation tests. 2026-03-19 10:00:01 -04:00
Thomas Harte 333c50f5b1 Test and correct branches. 2026-03-18 17:35:55 -04:00
Thomas Harte 0c55aa53e9 Extended tests and corrections as far as JSR. 2026-03-18 17:16:55 -04:00
Thomas Harte 6487e10e22 Fill in extension counts. 2026-03-18 11:31:09 -04:00
Thomas Harte 814b50ccbf Start to introduce costed performances. 2026-03-18 11:11:30 -04:00
Thomas Harte d787af89c5 Write ADDD result back. 2026-03-16 15:03:48 -04:00
Thomas Harte d4f89888c9 Fix ADC flags. 2026-03-16 14:48:23 -04:00
Thomas Harte 69823ac117 Correct various subtraction flags. 2026-03-16 14:43:11 -04:00
Thomas Harte da2f9aab1c Fix MUL flags. 2026-03-16 14:30:14 -04:00
Thomas Harte 38b00373c2 LEA operates differently than LD with regard to flags. 2026-03-16 12:28:11 -04:00
Thomas Harte 4aad105c54 Limit CC testing where helpful. 2026-03-16 11:29:02 -04:00
Thomas Harte e1b5c5b8da Ensure low DAA addition rolls over into high. 2026-03-16 11:18:37 -04:00
Thomas Harte 84b5292f0a Don't let a JMP target set flags. 2026-03-16 11:00:22 -04:00
Thomas Harte ec1595a55c Fix LSL overflow. 2026-03-16 10:56:26 -04:00
Thomas Harte 7c3211a835 Correct carry after NEG. 2026-03-16 10:40:06 -04:00
Thomas Harte df9ff6085c Introduce category for irregular operations; implement PUL. 2026-03-14 23:36:18 -04:00
Thomas Harte 91a9c90f9c Fix immediate 8 -> 16 mapping step. 2026-03-14 16:33:28 -04:00
Thomas Harte d15fbe91bb Implements SUBs and CMPs. 2026-03-12 23:09:49 -04:00
Thomas Harte 8a95da16e2 Implement DAA, ST, ROL/ROR. 2026-03-12 22:53:22 -04:00
Thomas Harte fe00e76d23 Add NEG, COM. 2026-03-12 22:34:22 -04:00
Thomas Harte b35b1b7dca Expand bitwise, basic arithmetic. 2026-03-12 22:26:16 -04:00
Thomas Harte 1b7fa8b053 Make sense of the task ahead. 2026-03-12 15:30:18 -04:00
Thomas Harte f242aacf05 Implement BIT, CLR and NOP. 2026-03-12 15:22:12 -04:00
Thomas Harte 70a4860f04 Implement MUL. 2026-03-11 21:47:21 -04:00
Thomas Harte 3704f008c6 Implement branching logic. 
I'm still sweeping timing under the rug for now.
 2026-03-11 17:26:22 -04:00
Thomas Harte 61bf62005c Implement shifts. 2026-03-11 15:45:00 -04:00
Thomas Harte a9358d3039 Start to flesh out operations. 2026-03-11 15:09:46 -04:00
Thomas Harte 68bba9e83f Add EXG as a freebie. 2026-03-11 09:52:44 -04:00
Thomas Harte 13745c6a6a Implement TFR. 
Albeit with most of the condition code register still absent.
 2026-03-10 22:58:33 -04:00
Thomas Harte ee40b99e11 Add some basic condition codes. 2026-03-10 19:07:01 -04:00
Thomas Harte 606063014b Start to bifurcate 8- and 16-bit immediate; tentatively begin 'perform' framework. 2026-03-10 17:30:21 -04:00