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Author SHA1 Message Date
Thomas Harte
b0a7c58287 Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents. 2017-06-04 17:57:37 -04:00
Thomas Harte
d2637123c4 Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software. 2017-06-04 17:55:19 -04:00
Thomas Harte
02b7c3d1b0 Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target. 2017-06-04 17:04:06 -04:00
Thomas Harte
8c1769f157 Made a quick attempt at serialising from ZX80 .O to waves. 2017-06-04 16:59:26 -04:00
Thomas Harte
655809517c Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required. 2017-06-04 16:37:03 -04:00
Thomas Harte
2190f60a89 Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool. 2017-06-04 15:46:35 -04:00
Thomas Harte
18faebc93c Merge pull request #130 from TomHarte/Bits35 
Corrects bit 3 & 5 emulation for everything except BIT n, (HL)
 2017-06-04 15:42:22 -04:00
Thomas Harte
0eebfdb4cc Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines. 2017-06-04 15:39:37 -04:00
Thomas Harte
7811374b0f Started sneaking in memptr emulation, hopefully to get to a working BIT (hl). 2017-06-04 15:07:07 -04:00
Thomas Harte
a2f01b4a46 Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now. 2017-06-04 14:59:18 -04:00
Thomas Harte
f5c910beb7 Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE. 2017-06-04 14:18:04 -04:00
Thomas Harte
4e014ca748 Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100? 2017-06-04 14:13:38 -04:00
Thomas Harte
87095b0578 Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures. 2017-06-04 14:04:26 -04:00
Thomas Harte
fba6ac2b4c Merge pull request #129 from TomHarte/TestMachineCommonality 
Generalises the Z80 test machine's trap handler also to cover the 6502
 2017-06-03 22:27:55 -04:00
Thomas Harte
1a811b1ab1 Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class. 2017-06-03 22:19:35 -04:00
Thomas Harte
c26349624c This, of course, should be inline to gain any benefit from the slightly-tortured private implementation. 2017-06-03 22:00:57 -04:00
Thomas Harte
b642d9f712 Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs. 2017-06-03 21:54:42 -04:00
Thomas Harte
fd6623b5a5 Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502. 2017-06-03 21:22:16 -04:00
Thomas Harte
0b2a3f18bc Merge pull request #128 from TomHarte/Scheduling 
Eliminates the micro-op scheduler
 2017-06-03 20:32:39 -04:00
Thomas Harte
b304c3a4b9 Eliminated the 6502's reliance on the micro-op scheduler. 2017-06-03 20:30:07 -04:00
Thomas Harte
3ceef2005b Pulled the Z80 from the MicroOpScheduler inheritance tree as it barely uses the thing, and that allows me to make the MicroOp structure private. 2017-06-03 19:17:34 -04:00
Thomas Harte
0f438f524b Merge pull request #124 from TomHarte/Z80 
Introduces a decent but as-yet-imperfect implementation of the Z80 processor.
 2017-06-03 19:11:21 -04:00
Thomas Harte
24c84ca6f5 Commented out as-yet-unimplemented features. 2017-06-03 19:10:23 -04:00
Thomas Harte
7898f643ac Added bus request/acknowledge logic. 2017-06-03 19:09:47 -04:00
Thomas Harte
7bd45d308a Error was simply failure of the interrupt-mode setter. Fixed. 2017-06-03 18:58:13 -04:00
Thomas Harte
b3da16911f Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2. 2017-06-03 18:42:54 -04:00
Thomas Harte
e52892f75b Added a test of interrupt mode 1. 2017-06-03 18:16:13 -04:00
Thomas Harte
8c41a0f0ed Added a test to confirm interrupts are disabled, and a response to the interrupt cycle within the all-RAM machine. 2017-06-03 17:53:44 -04:00
Thomas Harte
3e9212aaff Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed. 2017-06-03 17:41:45 -04:00
Thomas Harte
a2ec902773 Made an attempt at implementing all three modes of IRQ. 2017-06-03 17:07:05 -04:00
Thomas Harte
1c0130fd02 Cleaned up with a macro, and decided to make absolutely sure that DecodeOperation is functioning as intended by removing the MoveToNextProgram from fetch-decode-execute. 2017-06-03 12:19:25 -04:00
Thomas Harte
3e3d6f97f4 Edged towards being able to implement interrupt mode 0: created a special-case micro-op for incrementing the PC, and formalised that DecodeOperation is a terminal operation. 2017-06-03 12:16:21 -04:00
Thomas Harte
9c3bda0111 Attempted to round out NMI handling. 2017-06-03 11:30:12 -04:00
Thomas Harte
d14902700a Minor syntax and wiring fixes. 2017-06-01 22:33:05 -04:00
Thomas Harte
c95c32a9fe Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine. 2017-06-01 22:31:04 -04:00
Thomas Harte
35e045d7a7 Made a first attempt at the correct segue into the three main kinds of interrupt, though the programs aren't written yet. So undefined behaviour would abound were an interrupt to occur. But it lets me figure out what effect the check has on performance. I hope little. 2017-06-01 22:16:22 -04:00
Thomas Harte
084e1f3d51 Added a latching of interrupt status before each bus operation, and reset and power-on inputs. 2017-06-01 21:40:08 -04:00
Thomas Harte
5b43cefb85 Started filling an appropriate mask variable with the interrupt request status right now. Which is step one towards implementing interrupts. 2017-06-01 20:34:52 -04:00
Thomas Harte
aab637c9e7 Made check_address_for_trap inlineable. 2017-06-01 18:28:34 -04:00
Thomas Harte
7d9b197383 Pulled the .get() call for fetch-decode-execute out of the main loop. 2017-06-01 18:28:04 -04:00
Thomas Harte
c9dd267ec1 Sketched an interface for signalling interrupts and pulled out some of the repetition in flag setting from ADD/ADC/SUB/SBC/CP. 2017-05-31 22:51:32 -04:00
Thomas Harte
a5254989f8 Rewired the Z80 not to use the program queue, as it's not proven a useful abstraction in practice and doing so yields an immediate 22% speed increase. 2017-05-31 20:15:56 -04:00
Thomas Harte
494ce073b5 Tests having been fixed by instating proper Z80 cycle counting, removed caveman logging. 2017-05-31 19:58:57 -04:00
Thomas Harte
b99e4210ba Eliminated pointless abstraction; I ended up going indirect on instruction pages rather than scheduling methods. 2017-05-31 19:57:03 -04:00
Thomas Harte
d3b74cbc91 Set proper initial value for number_of_cycles_. 2017-05-31 19:55:51 -04:00
Thomas Harte
5ff73faf48 Ensured Zexall can pass. 2017-05-31 19:55:06 -04:00
Thomas Harte
2f7f11e2e5 Added diagnosis props. 2017-05-31 06:54:25 -04:00
Thomas Harte
5119997122 Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function. 2017-05-30 22:41:23 -04:00
Thomas Harte
b5c1773d59 Eliminated another conditional. Albeit a very predictable one. 2017-05-30 22:15:43 -04:00
Thomas Harte
dfb5057342 Moved repetition group conditions explicitly into the switch statement. 2017-05-30 22:12:10 -04:00