Thomas Harte
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42b5b66305
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Remove the 6502's use of runtime polymorphism in favour of ordinary templating.
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2017-08-16 11:56:52 -04:00 |
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Thomas Harte
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3947347d88
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Introduces active input handling for the AY and uses it in the CPC to give proper, active keyboard input, rather than push-on-select, which was only ever a temporary hack. Also maps a few more keys for the Amstrad.
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2017-08-15 22:47:17 -04:00 |
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Thomas Harte
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bbb17acf3a
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Expanded interface so that an external machine caller can request a string be typed without any knowledge of whatever it intends to do re: CharacterMappers. Which is immediately useful in paste functionality.
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2017-08-03 11:50:50 -04:00 |
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Thomas Harte
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ad3a98387f
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Within the Typer framework: hatched out CharacterMapper as a distinct thing from the target for keypresses, better to formalise responsibility but also to make it easy cleanly to sever that stuff into its own little part.
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2017-08-03 11:42:31 -04:00 |
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Thomas Harte
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e6854ff8db
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Corrected typo: the input to an AY is BDIR, not BCDIR.
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2017-08-01 17:06:57 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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279c369a1f
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Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.
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2017-07-25 22:21:09 -04:00 |
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Thomas Harte
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296c7cec05
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Adopted flush widely.
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2017-07-25 20:42:51 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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a1e9a54765
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Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
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2017-07-25 20:09:13 -04:00 |
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Thomas Harte
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c1527cc9e2
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Reduced back-and-forth between Cycles and ints within the Oric.
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2017-07-24 22:46:31 -04:00 |
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Thomas Harte
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efdac2ce8c
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The 6522 is now a ClockReceiver.
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2017-07-24 22:29:09 -04:00 |
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Thomas Harte
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55ecb0c022
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Converted the Microdisc into a ClockReceiver.
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2017-07-24 21:51:13 -04:00 |
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Thomas Harte
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b7f88e8f61
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Filter is now a ClockReciever, affecting all sound output devices.
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2017-07-24 21:29:13 -04:00 |
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Thomas Harte
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8a2bdb8d22
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Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
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2017-07-24 21:19:05 -04:00 |
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Thomas Harte
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b82bef95f3
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Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
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2017-07-24 20:10:05 -04:00 |
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Thomas Harte
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6369138bd1
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Converted the Oric's video output into a ClockReceiver.
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2017-07-22 23:11:30 -04:00 |
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Thomas Harte
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2ff157cf7a
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Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.
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2017-07-22 22:17:29 -04:00 |
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Thomas Harte
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83628b285b
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Experimentally turned the 6502 into a clock receiver. No problem encountered.
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2017-07-22 21:52:21 -04:00 |
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Thomas Harte
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3f609e17b3
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Factored out the table-lookup approach to being a typer, and adjusted so as definitely to limit myself to positive offset table lookups.
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2017-07-21 21:18:51 -04:00 |
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Thomas Harte
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52d9ddf9e5
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Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue.
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2017-06-21 22:13:24 -04:00 |
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Thomas Harte
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2562306802
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Merge branch 'master' into Z80
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2017-05-16 21:05:00 -04:00 |
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Thomas Harte
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a5075d9eb5
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Formalised the reasoning behind the colour phase fix-up and made it an opt-in per-caller value. Only the Oric currently needs to opt in.
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2017-05-16 20:31:39 -04:00 |
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Thomas Harte
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eb8a2de5d6
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Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
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2017-05-15 07:38:59 -04:00 |
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Thomas Harte
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0808e9b6fb
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Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.
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2017-05-14 22:08:15 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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90151e2094
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Fixed to ensure a known initial control register value, which has taken effect.
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2016-12-28 18:49:32 -05:00 |
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Thomas Harte
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a568172758
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Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.
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2016-12-28 18:29:37 -05:00 |
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Thomas Harte
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e62be03673
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Removed endianness assumption.
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2016-12-10 19:10:33 -05:00 |
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Thomas Harte
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a5683dfb21
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Removed now untrue comment.
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2016-12-10 15:19:48 -05:00 |
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Thomas Harte
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0e71802b92
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Reduced Oric video to single nibble constants. Removed attempt at asynchronous flush as no longer required.
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2016-12-10 14:17:46 -05:00 |
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Thomas Harte
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580f347727
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Fixed Oric SCART mode by having it change what it's giving to the CRT based on which shader it knows will be active.
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2016-12-10 13:55:56 -05:00 |
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Thomas Harte
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a549fd1ecc
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Introduced the ability simply to piggy-back off the CRT's natural phase for the colour burst, thereby eliminating a couple of redundant independent attempts in the Oric and Electron.
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2016-12-10 13:42:34 -05:00 |
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Thomas Harte
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6cdd41e5a9
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Added direct use of the colour ROM, uploading 16 bits per pixel to contain the entire ROM composite wave.
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2016-12-09 22:17:10 -05:00 |
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Thomas Harte
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3b5962b171
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This is an initial attempt at using the actual Oric colour ROM values for composite video generation.
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2016-12-09 20:01:27 -05:00 |
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Thomas Harte
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c304db0f5a
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Deintegrated the busy flag and the interrupt request line, as the latter is reset by status reads. Which also means I can start reporting the WD INTRQ line status directly from the Microdisc. That appears to be correct, rather than honouring the Microdisc IRQ select there.
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2016-12-06 21:16:29 -05:00 |
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Thomas Harte
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2003b514aa
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Switched the typer to postfix underscores.
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2016-12-03 10:55:50 -05:00 |
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Thomas Harte
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81ee834530
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As well as a bunch of logging, reinstated rotation position preservation across tracks.
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2016-12-02 18:36:47 -05:00 |
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Thomas Harte
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93c573bfa9
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Implemented missing status bits (other than the index hole), and a head loading delay for the Microdisc.
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2016-12-01 21:13:16 -05:00 |
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Thomas Harte
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442986ee2c
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Introduced a head loading path for 1793 machines.
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2016-12-01 20:12:22 -05:00 |
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Thomas Harte
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82899f2f47
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Ensured flag setting is atomic, removed duplication of interrupt request versus busy, found better names for the personality testers, unified delegate protocol.
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2016-12-01 07:41:52 -05:00 |
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Thomas Harte
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9b6c5e814a
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Now that it can be more explicit, this should admit that it's '93-based, not '73.
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2016-11-28 16:22:35 -05:00 |
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Thomas Harte
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2f459690d4
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It would appear the 1770 and 1773 actually differ in relation to the (non-sensical) ability not to spin-up for a Type 2, and whether a side compare can occur. So the WD1770 class now requires a personality to be specified. Which it singly fails to honour.
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2016-11-26 23:29:30 +08:00 |
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Thomas Harte
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e9d6566e9c
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Of course, changing the IRQ enable may immediately change the IRQ line. Signal if so.
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2016-11-26 09:35:44 +08:00 |
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Thomas Harte
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73d30b9c00
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Corrected typo.
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2016-11-25 21:30:45 +08:00 |
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Thomas Harte
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12956901d6
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Filled in some register mirrors.
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2016-11-25 21:28:11 +08:00 |
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Thomas Harte
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54246c8f1a
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Interrupt enabling works the other way around I think, and both registers with only one bit defined should probably return '1' in all other places?
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2016-11-25 21:24:59 +08:00 |
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Thomas Harte
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8be81f6ebd
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Supplied disks are given to the Microdisc.
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2016-11-25 20:53:38 +08:00 |
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Thomas Harte
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4af678d2ed
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Gave the Microdisc a clock signal, added just enough of force interrupt to avoid a spurious belief that a type 3 command has started.
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2016-11-25 20:51:39 +08:00 |
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