23 Commits

Author	SHA1	Message	Date
Thomas Harte	1c154131f9	Expands size of storage in Cycles/HalfCycles; adjusts widely to compensate.	2019-10-29 22:36:29 -04:00
Thomas Harte	a5057e6540	Ensures that stop means stop.	2019-10-28 22:12:45 -04:00
Thomas Harte	cf37e9f5de	Remove source control markers.	2019-10-20 23:40:51 -04:00
Thomas Harte	e4f7ead894	Merge branch 'AtariST' of github.com:TomHarte/CLK into AtariST	2019-10-20 23:40:01 -04:00
Thomas Harte	4134463094	The ACIA now receives bits.	2019-10-20 23:34:30 -04:00
Thomas Harte	83d73fb088	The keyboard now responds to a reset on its serial line.	2019-10-20 23:13:44 -04:00
Thomas Harte	cf07982a9b	Ensures good serial line and ACIA behaviour. ... Next stop: having the intelligent keyboard react.	2019-10-20 22:10:05 -04:00
Thomas Harte	2e86dada1d	Ensures updates even when the event queue is empty.	2019-10-20 20:38:56 -04:00
Thomas Harte	696af5c3a6	Starts to transfer serial line decoding logic into the line itself.	2019-10-20 20:38:56 -04:00
Thomas Harte	9a8352282d	Mostly but not quite fixes serial work.	2019-10-20 20:38:55 -04:00
Thomas Harte	34075a7674	Attempts to tie an intelligent keyboard to the other end of its serial line.	2019-10-20 20:38:55 -04:00
Thomas Harte	d461331fd2	Ensures remaining_delays_ is set properly after [reset/flush]_writing.	2019-10-20 20:38:55 -04:00
Thomas Harte	374439693e	Ensures serial lines know their writer's clock rate.	2019-10-20 20:38:55 -04:00
Thomas Harte	4e5b440145	Attempts mostly to implement 6850 output.	2019-10-20 20:38:55 -04:00
Thomas Harte	2bd7be13b5	Decodes the 6850 control register, and starts working on standardised serial ports.	2019-10-20 20:38:55 -04:00
Thomas Harte	e095a622d3	Ensures updates even when the event queue is empty.	2019-10-17 23:59:43 -04:00
Thomas Harte	9ab49065cd	Starts to transfer serial line decoding logic into the line itself.	2019-10-17 23:34:39 -04:00
Thomas Harte	f5a2e180f9	Mostly but not quite fixes serial work.	2019-10-16 23:34:37 -04:00
Thomas Harte	0fd8813ddb	Attempts to tie an intelligent keyboard to the other end of its serial line.	2019-10-16 23:21:14 -04:00
Thomas Harte	3b165a78f2	Ensures remaining_delays_ is set properly after [reset/flush]_writing.	2019-10-13 21:39:25 -04:00
Thomas Harte	f86dc082bb	Ensures serial lines know their writer's clock rate.	2019-10-13 20:41:08 -04:00
Thomas Harte	8b50a7d6e3	Attempts mostly to implement 6850 output.	2019-10-12 23:14:29 -04:00
Thomas Harte	4bf81d3b90	Decodes the 6850 control register, and starts working on standardised serial ports.	2019-10-12 18:19:55 -04:00