1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-29 12:50:28 +00:00
Commit Graph

163 Commits

Author SHA1 Message Date
Thomas Harte
f3d3e588fd Add enough of state to [sort-of] pass the first test.
i.e. until the processor overruns, as it is permitted to do, and can't handle the second instruction.
2022-05-17 16:51:26 -04:00
Thomas Harte
4a40581deb Completes performance of NBCD D0. 2022-05-17 16:10:20 -04:00
Thomas Harte
eed2672db5 Add documentation, honour signal_will_perform. 2022-05-17 15:05:11 -04:00
Thomas Harte
84071ac6d0 Implement reset logic, advance as far as actually performing an NBCD on D0 (but not writing it back). 2022-05-17 14:51:49 -04:00
Thomas Harte
1a27eea46c Establish general pattern for selecting a performance phase and obtaining operands. 2022-05-17 14:08:50 -04:00
Thomas Harte
d0b6451f02 Step gingerly on to fetching operands. 2022-05-17 08:26:35 -04:00
Thomas Harte
2147c5a5f2 Fill in missing #undefs. 2022-05-16 21:02:25 -04:00
Thomas Harte
c7aa4d8b6d Fix state transitions.
Confirmed that the 68000 mk 2 now appears correctly to perform a reset.
2022-05-16 21:00:25 -04:00
Thomas Harte
e94efe887c Switch to use of __COUNTER__. 2022-05-16 20:38:17 -04:00
Thomas Harte
3db2de7478 Works 68000 mk2 into the comparative tests.
... revealing that I've leant a little too hard on __LINE__.
2022-05-16 20:04:13 -04:00
Thomas Harte
345f7c3c62 Fill in just enough to attempt the reset exception, assuming DTACK rather than VPA or BERR. 2022-05-16 16:57:40 -04:00
Thomas Harte
6f6e466c08 Make a first sketch of the coroutine-esque structure I'm going to experiment with here. 2022-05-16 11:59:03 -04:00
Thomas Harte
b0518040b5 Plants the seek of a 68000 mark 2. 2022-05-16 11:44:16 -04:00