6502/CLK
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mirror of https://github.com/TomHarte/CLK.git synced 2026-10-24 18:02:22 +00:00
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14,636 Commits 6 Branches 152 Tags
10597ed8301ac46d0f5b01cdc4e2c469cc180298
Commit Graph
1753 Commits
Author SHA1 Message Date
Thomas Harte 43bed7406d Field sync runs from end of display to end of sync. 2026-05-12 15:27:10 -04:00
Thomas Harte 8b1c1e9c7a Add TODO. 2026-05-12 15:09:23 -04:00
Thomas Harte 0fb2490af5 As implemented, the delegate need not be dynamic. 2026-05-12 15:03:30 -04:00
Thomas Harte 9ec7e39874 Add delegate call-outs. 2026-05-12 14:53:52 -04:00
Thomas Harte 91ec4012b9 Don't impose NTSC colour bursts on PAL. 2026-05-12 14:07:10 -04:00
Thomas Harte f7bf10698c Switch 'colour' palettes. 2026-05-12 12:32:07 -04:00
Thomas Harte c55bccb215 Attempt full accounting for 6847 modes. 2026-05-12 12:25:12 -04:00
Thomas Harte c2e7e2f796 Apply MSB to semigraphics connection. 2026-05-12 11:34:23 -04:00
Thomas Harte 72fbd34ba3 Adjust means of mode capture. 2026-05-12 11:28:33 -04:00
Thomas Harte 716f06b1f2 Tweak colour-burst phase. 2026-05-07 15:07:12 -04:00
Thomas Harte ef494af270 Do _something_ for pixel modes. 2026-05-07 14:41:15 -04:00
Thomas Harte 779b370796 Make 6847 just-in-time; wire through IRQs. 2026-05-06 17:31:03 -04:00
Thomas Harte 276238895e Implement next_sequence_point. 2026-05-06 17:14:16 -04:00
Thomas Harte 60f79720f2 Start clarifying interface. 2026-05-06 17:05:34 -04:00
Thomas Harte 197a79192d Expose h/vsync getters. 2026-05-06 16:27:03 -04:00
Thomas Harte 05f0f4fbdf Add TODOs on remaining work. 2026-05-06 14:44:12 -04:00
Thomas Harte c60e19eadd Wire 6847 accesses through SAM. 2026-05-06 14:38:11 -04:00
Thomas Harte e71504f298 Configure address generation as per mode. 2026-05-06 14:32:54 -04:00
Thomas Harte f9d25b5f93 Fix to post hoc address increment. 2026-05-06 12:41:36 -04:00
Thomas Harte e51cdd14b2 On further reading: the 6883 and 6847 use different address logic. 2026-05-06 12:05:25 -04:00
Thomas Harte 1d3c4ca51a Include a colour burst. 2026-05-05 21:40:32 -04:00
Thomas Harte 3798153ceb Implement probably-correct line timings. 2026-05-05 21:32:58 -04:00
Thomas Harte 03ccc8186a This probably still isn't correct, but restores text. 2026-05-05 15:25:40 -04:00
Thomas Harte af56b00ce0 It'll be in two places, so start an independent address counter. 2026-05-05 11:47:10 -04:00
Thomas Harte 1af2b1f24e Hard code way into actual character display. 2026-05-04 20:52:11 -04:00
Thomas Harte 2bed78886b Guess at line timing. 2026-05-04 20:41:55 -04:00
Thomas Harte 2e014f5363 Get to a stable display of vertical lines. 2026-05-04 20:35:38 -04:00
Thomas Harte 08ec74824c Resolve horizontal timing errors. 2026-05-04 16:53:42 -04:00
Thomas Harte 832a031b80 Build faulty frame logic. 2026-05-04 16:46:37 -04:00
Thomas Harte f6eece09b5 Import default font. 2026-05-04 12:29:15 -04:00
Thomas Harte c2d1a94f07 Add file for 6847. 2026-05-04 12:22:15 -04:00
Thomas Harte 04cd3a420c Rename get -> as for project consistency. 2026-05-01 14:04:16 -04:00
Thomas Harte 8f9b57a560 Correct asserts. 2026-04-18 09:21:36 -04:00
Thomas Harte 1ef7744907 Fix row filling, add some asserts. 2026-04-18 08:50:18 -04:00
Thomas Harte 587258518d Merge branch 'master' into MasterSystemMap 2026-04-18 08:36:43 -04:00
Thomas Harte 940708bd07 Support floating bus going either way. 2026-04-16 21:52:10 -04:00
Thomas Harte 363072078b Add TODO, remove TODO. 2026-04-12 09:26:03 -04:00
Thomas Harte f118fd0c48 Zero-initialise sub_row. 2026-04-11 09:25:57 -04:00
Thomas Harte 29983c06fc Reformat mildly. 2026-04-10 19:32:28 -04:00
Thomas Harte 649b70dc2d Correct fixed-right row info. 2026-04-10 16:50:25 -04:00
Thomas Harte 99a1fd6c1e Log if data isn't being read. 2026-04-06 21:40:56 -04:00
Thomas Harte 02c17a5b53 Apply what a schematic seems to imply. 2026-04-04 22:38:03 -04:00
Thomas Harte 8c357bd6dd Expand toggle into a full-on DAC. 2026-03-28 23:10:55 -04:00
Thomas Harte 05a85b6ba9 Resolve various compiler warnings: primarily ~'s promotion to int. 2026-03-25 13:57:32 -04:00
Thomas Harte fa136b89fa Do enough of C2 output to catch the tape motor. 2026-03-23 16:23:34 -04:00
Thomas Harte 66af2c00a8 Add TODO. 2026-03-22 23:06:19 -04:00
Thomas Harte 1be89a3dd5 Fix 6821 read decoding; keyboard is now being scanned. 2026-03-22 19:48:56 -04:00
Thomas Harte 2a1d9bc8e4 Try: storage is in control register, but is not writeable. 2026-03-20 16:41:03 -04:00
Thomas Harte 3913a2c9d3 Switch comprehension of what combines to make IRQA and B. 2026-03-20 14:45:56 -04:00
Thomas Harte e098a5d08d Attempt wiring of interrupts. 2026-03-20 13:24:05 -04:00