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Commit Graph

72 Commits

Author SHA1 Message Date
Thomas Harte
a43ada82b2 Experiments with a JustInTimeActor in the Master System. 2019-07-29 15:38:41 -04:00
Thomas Harte
ee8d853fcb Ensures you can't get a phase 2 for free with run_for(0). 2019-07-17 14:20:27 -04:00
Thomas Harte
245e27c893 Solidifies belief that the shift register bit is cleared on read/write. 2019-07-08 16:45:15 -04:00
Thomas Harte
28de629c08 Fixes the 6522 sufficiently to fix keyboard input. 2019-07-08 15:29:34 -04:00
Thomas Harte
210bcaa56d Introduces an initial shift unit test, and makes it pass. 2019-07-07 22:13:36 -04:00
Thomas Harte
9230969f43 Corrects enough of the 6522 and Keyboard to get an initial command seemingly working. 2019-06-10 09:28:27 -04:00
Thomas Harte
0e16c67805 Improves shift register connection, towards having the keyboard function properly.
It now seems not to receive a command terminator, but is at least getting a command.
2019-06-08 23:04:55 -04:00
Thomas Harte
abe55fe950 Adds Timer 1 toggling of PB7. 2019-06-03 15:39:20 -04:00
Thomas Harte
723137c0d4 With some time additions to the 6522, starts wiring in Macintosh audio.
The audio buffer is also the disk motor buffer, so this is preparatory to further disk work.
2019-06-01 14:39:40 -04:00
Thomas Harte
8293b18278 Adds a TODO on what I think might be an incorrect implementation? 2019-05-08 15:06:40 -04:00
Thomas Harte
2ba0364850 Adds the shift register interrupt. 2019-05-08 15:02:07 -04:00
Thomas Harte
2e7bc0b98a Attempts the shift register. 2019-05-08 14:54:40 -04:00
Thomas Harte
8278809383 Attempts to get more rigorous on communicating outward control line changes. 2019-05-08 13:33:22 -04:00
Thomas Harte
4367459cf2 Takes a first go at handshake and pulse modes. 2019-05-08 12:48:29 -04:00
Thomas Harte
254132b83d Eliminates 6522Base in pursuit of working handshake modes.
Specifically: this means that the places from which the BusHandler may be called are more numerous.
2019-05-08 12:35:17 -04:00
Thomas Harte
7e6d4f5a3e Adds emulation of the real-time clock. 2019-05-08 00:12:19 -04:00
Thomas Harte
d97348dd38 Eliminates dangling uses of printf. 2019-03-02 18:07:05 -05:00
Thomas Harte
0b771ce61a Removes all instances of the copyright symbol. 2018-05-13 15:19:52 -04:00
Thomas Harte
bc464e247f The 1540 and, by extension, the Vic-20 are now activity sources. 2018-05-11 22:24:33 -04:00
Thomas Harte
edb9fd301c Begins this project's conversion to functional-style casts. 2017-10-03 22:04:15 -04:00
Thomas Harte
ff510f3b84 Explicitly disallows copying of VIAs, and marks the constructor as noexcept. 2017-09-05 21:21:23 -04:00
Thomas Harte
7fd6699e0b Corrects comment indentation. 2017-09-05 21:15:15 -04:00
Thomas Harte
450712f39c Improves and corrects 6522 header documentation. 2017-09-04 14:32:34 -04:00
Thomas Harte
24b3faa427 Deconstitutes the 6522 into component parts, templated and non-templated.
Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
2017-09-04 14:26:04 -04:00
Thomas Harte
4abd62e62b Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty. 2017-07-27 22:05:29 -04:00
Thomas Harte
1da24d10fd Corrected a couple of build errors. 2017-07-27 08:05:14 -04:00
Thomas Harte
8361756dc4 Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock. 2017-07-27 07:40:02 -04:00
Thomas Harte
75d67ee770 Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts. 2017-07-25 20:20:55 -04:00
Thomas Harte
efdac2ce8c The 6522 is now a ClockReceiver. 2017-07-24 22:29:09 -04:00
Thomas Harte
e01f3f06c8 Completed curly bracket movement. 2017-03-26 14:34:47 -04:00
Thomas Harte
36bc558798 Converted all 'Components' to postfix underscores. 2016-12-03 10:51:09 -05:00
Thomas Harte
fa65cc2058 Resolved type conversion error. 2016-11-05 12:57:01 -04:00
Thomas Harte
30c670f8de Ensured programmatic setting of the timers occurs during phase 2 _instead_ of counting. 2016-11-04 21:30:18 -04:00
Thomas Harte
ad00304e8a Fixed 6522 countdown. 2016-10-28 21:05:42 -04:00
Thomas Harte
4fab794747 Added a direct-to-two-cycles emulation path for 6522 owners. 2016-10-27 21:13:25 -04:00
Thomas Harte
2eda0b3c86 Attempted to simplify the logic behind the most common 6522 usage. 2016-10-27 21:06:31 -04:00
Thomas Harte
b43a7381ae Fixed framing and first-byte-after-sync signalling. Hacked together as parts of it are, loading now appears to work! 2016-08-01 04:25:11 -04:00
Thomas Harte
11cd541786 Fixed accidental indentation. 2016-07-10 08:05:05 -04:00
Thomas Harte
c0ab45a73d Disabled a bunch of the caveman debug logging. 2016-07-09 22:29:11 -04:00
Thomas Harte
7cc4bf3fe7 Hit and hope is getting me nowhere. Time to unit test this thing. 2016-07-09 15:40:25 -04:00
Thomas Harte
1baf21827c Since the ROM is well disassembled, let's actually try to be a 1541 first. 2016-07-06 22:17:32 -04:00
Thomas Harte
8819711bc8 Threw in the second VIA as a currently clearly incorrect thing. 2016-07-05 22:22:09 -04:00
Thomas Harte
602e7f01c7 Control lines seem to have evolved to pure push. 2016-07-05 21:15:29 -04:00
Thomas Harte
93c2bb80a2 Improved a comment, added independent C[A/B]2 input mode. 2016-07-05 21:11:51 -04:00
Thomas Harte
1bb109a23b Made a quick attempt at basic C[A/B]2 interrupts. 2016-07-05 20:39:15 -04:00
Thomas Harte
c3b7d24293 It appears that the attention line is also wired to CB2. So the ball is back in the 6522's court. 2016-07-05 19:19:46 -04:00
Thomas Harte
97751a9d86 Took the preliminary steps necessary to wire up a serial port. 2016-07-05 10:55:47 -04:00
Thomas Harte
82b0bc9b58 Discovered that this is another meaningful usage of using. 2016-07-04 19:10:10 -04:00
Thomas Harte
7fa010a463 Attempted to add support for the most basic of control line output, and slightly to optimise the Vic. 2016-07-01 19:01:22 -04:00
Thomas Harte
69d78dfdb3 Removed logging. 2016-06-26 21:36:26 -04:00