104 Commits

Author	SHA1	Message	Date
Thomas Harte	18ffb9294f	Add full cursor automation.	2024-05-12 22:16:29 -04:00
Thomas Harte	6d42c9aaf9	Start making leeway on interesting SWIs.	2024-05-06 22:40:00 -04:00
Thomas Harte	02ee3a7804	Turf out old debugging cruft.	2024-05-06 20:36:00 -04:00
Thomas Harte	42aea2663c	Add automatic runtime frame-rate limiter.	2024-04-30 21:38:37 -04:00
Thomas Harte	71c5a1d419	Avoid repeated trans comparison.	2024-04-29 22:35:01 -04:00
Thomas Harte	5a84e98256	Fix trans for instruction fetches.	2024-04-29 21:54:59 -04:00
Thomas Harte	becb6ce2e0	Fix two more not-really-an-issue warnings.	2024-04-23 22:20:13 -04:00
Thomas Harte	265d151879	Fix data aborts.	2024-04-22 22:08:09 -04:00
Thomas Harte	ea3eef3817	Put interrupts into pipeline, without delay.	2024-04-19 22:21:23 -04:00
Thomas Harte	83eac172c9	Revoke in-pipeline interrupts. ... I'm unclear on what timing should apply here really.	2024-04-19 21:46:09 -04:00
Thomas Harte	5b13d3e893	Attempt the prefetch portion of a pipeline.	2024-04-19 21:30:15 -04:00
Thomas Harte	e6c4454059	Provide a means for SWI interception.	2024-04-18 22:13:58 -04:00
Thomas Harte	d464ce831a	Add did_set_pc.	2024-04-18 19:30:07 -04:00
Thomas Harte	07984a2f8b	Resolve various warnings.	2024-04-17 22:15:05 -04:00
Thomas Harte	fac94a5d36	Reduce MIPS. Until other performance issues can be resolved.	2024-04-16 22:32:00 -04:00
Thomas Harte	6ac6e48b95	Attempt audio output.	2024-04-13 21:54:50 -04:00
Thomas Harte	d9d675a74f	Fix scan status scale.	2024-04-09 21:56:42 -04:00
Thomas Harte	169298af42	Plumb through disk insertion. ... Surprisingly: some things now load.	2024-04-08 21:15:40 -04:00
Thomas Harte	4f58664f97	Catch interrupt enables.	2024-04-07 22:08:12 -04:00
Thomas Harte	d2b077c573	Start wiring in a floppy controller.	2024-04-07 21:22:35 -04:00
Thomas Harte	543b1c644a	Wire mouse events to the relevant class.	2024-04-06 13:32:59 -04:00
Thomas Harte	3f40e409c5	Reduce debugging heft.	2024-04-04 22:16:11 -04:00
Thomas Harte	7d8a364658	Reimplement LDM and STM.	2024-04-04 21:59:18 -04:00
Thomas Harte	609c117267	Switch to English RISC OS.	2024-04-01 21:44:42 -04:00
Thomas Harte	914b88d115	Fix non-debug build.	2024-03-31 19:17:55 -04:00
Thomas Harte	cc122a7a68	Add an SWI count, to aid in logging.	2024-03-31 18:18:26 -04:00
Thomas Harte	31979649c6	As it continues to swell, factor out the junk.	2024-03-31 18:15:48 -04:00
Thomas Harte	335d13d06d	Mildly improve logging, define a few more ROMs.	2024-03-30 21:49:21 -04:00
Thomas Harte	ec785f3a8a	Add URL as comment.	2024-03-30 20:54:17 -04:00
Thomas Harte	1f83a5425e	Complete list of all currently-failing SWIs. ... ... a lot of which are probably failing correctly, i.e. they're appropriately signalling.	2024-03-30 20:48:47 -04:00
Thomas Harte	4882d6d0f2	Start adding SWI detail.	2024-03-30 15:16:48 -04:00
Thomas Harte	722743659b	Add missing space.	2024-03-29 21:52:57 -04:00
Thomas Harte	6e64a79b52	Log failed SWIs.	2024-03-29 21:31:33 -04:00
Thomas Harte	8a6bf84cff	Keyboard: log more, ignore unrecognised commands.	2024-03-29 20:54:07 -04:00
Thomas Harte	f175dcea58	Hack in some more potential debugging help.	2024-03-27 22:37:37 -04:00
Thomas Harte	f46af4b702	OS 3.11 seems to be able to get into BASIC.	2024-03-25 22:10:35 -04:00
Thomas Harte	d2776071e4	Speed up debug mode.	2024-03-25 21:31:33 -04:00
Thomas Harte	72a645ec1e	Fix trans; take further crack at MEMC permissions.	2024-03-25 15:50:59 -04:00
Thomas Harte	1154ffd072	Add a 'drive in use' indicator LED.	2024-03-25 15:03:54 -04:00
Thomas Harte	8ba9708942	Hopefully resolve the mystery of the latch writes.	2024-03-25 14:54:30 -04:00
Thomas Harte	521fca6089	Expose full bus to IOC dependents; add notes.	2024-03-25 11:07:44 -04:00
Thomas Harte	6980fd760c	Add further heavily-manual debugging aids.	2024-03-24 22:18:30 -04:00
Thomas Harte	5ccb18225a	Provide key states to the keyboard.	2024-03-23 15:43:04 -04:00
Thomas Harte	9ea3e547ee	Fix IRQ/FIQ return addresses.	2024-03-22 21:42:34 -04:00
Thomas Harte	fb5fdc9f10	Actually apply video divider.	2024-03-22 10:24:24 -04:00
Thomas Harte	ae6cf69449	Move responsibility for clock division; reinstate vsync interrupt.	2024-03-22 10:01:34 -04:00
Thomas Harte	2de1a2dd0d	Install and properly clock a CRT.	2024-03-21 20:41:24 -04:00
Thomas Harte	40b5227f0b	Deliver all addresses to the video outputter.	2024-03-21 11:24:47 -04:00
Thomas Harte	2d6a4d490e	Add dummy retrace interrupt.	2024-03-21 10:02:56 -04:00
Thomas Harte	208f3e24de	Audio ticks are now included.	2024-03-20 14:30:21 -04:00