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6502/CLK
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mirror of https://github.com/TomHarte/CLK.git synced 2026-10-22 20:02:25 +00:00
Code Issues Projects Releases Wiki Activity
14,434 Commits 6 Branches 152 Tags
1ef7744907d4ec135b3676643db9a0595ca62d7e
Commit Graph
13 Commits
Author SHA1 Message Date
Thomas Harte 186b911e8e Switch to get/as. 2026-03-06 15:44:22 -05:00
Thomas Harte 0d1fe03369 Further prefer static constexpr. 2025-09-12 21:40:08 -04:00
Thomas Harte 23c67f7e38 Correct improper application of const. 2024-11-30 17:32:16 -05:00
Thomas Harte 3addb8d72b Finish updating components. 2024-11-30 17:21:00 -05:00
Thomas Harte 6b18d775ab Eliminate unused variables. 2024-03-12 21:53:26 -04:00
Thomas Harte a1a7c0e253 Apply maybe_unused judiciously. 2023-05-15 10:17:04 -04:00
Thomas Harte 2a7a42ff8f Add header for assert. 2021-11-24 16:28:18 -05:00
Thomas Harte 0ad1529f3f Retain delegate bit length for non-self-clocked data. 2021-11-24 16:15:27 -05:00
Thomas Harte 941d9a46a2 Makes a better effort at exposition; better implements clocked line. 2021-11-07 05:18:40 -08:00
Thomas Harte ecfe68d70f Introduce the principle that a Serial::Line can be two-wire — clock + data. 2021-11-06 16:54:20 -07:00
Thomas Harte f102d8a4b4 Extend to allow full-[byte/word/dword] writes, in LSB or MSB order. 2021-11-06 12:01:32 -07:00
Thomas Harte 25996ce180 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
Thomas Harte e3abbc9966 Renames what didn't end up being a whole SerialPort. 2019-11-09 15:21:51 -05:00
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