40 Commits

Author	SHA1	Message	Date
Thomas Harte	2912d7055b	The 6532 is now a ClockReceiver.	2017-07-24 21:57:24 -04:00
Thomas Harte	b3ae920746	Converted the DPLL and disk controller classes to be ClockReceivers.	2017-07-24 21:04:47 -04:00
Thomas Harte	e6578defcd	It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.	2017-07-23 22:22:50 -04:00
Thomas Harte	ace8e30818	Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.	2017-07-23 22:21:39 -04:00
Thomas Harte	b0c2325adc	Corrected run call, and accepted that jam handling is gone forever.	2017-07-22 22:21:26 -04:00
Thomas Harte	7b5f93510b	Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.	2017-07-16 20:55:57 -04:00
Thomas Harte	8ddd686049	Removed redundant variable.	2017-07-16 19:04:03 -04:00
Thomas Harte	2fb0aea990	Updated the C1540 test vessel to the new world.	2017-07-16 17:00:39 -04:00
Thomas Harte	95a6b0f85c	Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.	2017-06-22 21:09:26 -04:00
Thomas Harte	0e0ce379b4	Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.	2017-06-21 20:38:08 -04:00
Thomas Harte	36e8a11505	Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.	2017-06-21 20:32:08 -04:00
Thomas Harte	d668879ba6	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	b6f51474ff	Ensured that -description can handle the newly-captured bus actions.	2017-06-17 18:20:30 -04:00
Thomas Harte	cf795562bf	Continued filling in tests, fleshing out what the test machine captures as a result.	2017-06-15 20:59:59 -04:00
Thomas Harte	aed2827e7b	Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.	2017-06-12 22:22:00 -04:00
Thomas Harte	fd6623b5a5	Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.	2017-06-03 21:22:16 -04:00
Thomas Harte	3e9212aaff	Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.	2017-06-03 17:41:45 -04:00
Thomas Harte	d14902700a	Minor syntax and wiring fixes.	2017-06-01 22:33:05 -04:00
Thomas Harte	c95c32a9fe	Implemented the reset line program and disabled fictitious automatic power-on reset for the Z80 test machine.	2017-06-01 22:31:04 -04:00
Thomas Harte	5119997122	Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.	2017-05-30 22:41:23 -04:00
Thomas Harte	960de7bd7b	Marginally reduced test machine costs based on usage.	2017-05-30 11:59:07 -04:00
Thomas Harte	8bfaa487ce	Improved logging of bus operations and corrected placement of the OUT step in that repetition group; was otherwise outputting the wrong side of the B adjustment and therefore to the wrong port (if interpreted as 16 bit).	2017-05-29 17:13:24 -04:00
Thomas Harte	a6a4c5a936	Made an attempt to introduce checking of bus activity against the FUSE tests. Appears to suggest 54 new failures.	2017-05-29 15:57:27 -04:00
Thomas Harte	ed7b07c8b1	Made an attempt to implement HALT as an operation that merely leaves the PC in place, adding the Z80's output line. Included that flag in FUSE tests. Discovered that it does not think that HALT acts that way. Which is probably correct.	2017-05-29 11:54:27 -04:00
Thomas Harte	6575091a78	Fixed Z80's ownership of its fetch-decode-execute program, its habit of scheduling invalidly when hitting an unrecognised operation and the test machine's habit of dereferencing invalidly.	2017-05-22 21:50:34 -04:00
Thomas Harte	9e25d014d2	Made an attempt to log bus activity for comparison with FUSE results.	2017-05-22 19:49:38 -04:00
Thomas Harte	22afa509ca	Got to a parsing and towards an attempt to run FUSE tests.	2017-05-22 19:14:46 -04:00
Thomas Harte	d910405648	Added enough infrastructure to be able to react to the two CP/M calls this cares about.	2017-05-19 21:53:39 -04:00
Thomas Harte	62b432c046	Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes.	2017-05-19 21:20:28 -04:00
Thomas Harte	64d6ee1be5	Adjusted slightly to adapt to latest Swift warnings.	2017-05-17 07:49:48 -04:00
Thomas Harte	87a021ec2d	Made further attempt to get as fas as having the Z80 attempt to do something.	2017-05-16 22:19:40 -04:00
Thomas Harte	189317b80c	Added enough of a Z80 test machine to bridge up into Swift.	2017-05-16 22:05:42 -04:00
Thomas Harte	df80c37adb	Renamed TestMachine to TestMachine6502 since there's going to be multiple of them.	2017-05-15 08:18:57 -04:00
Thomas Harte	0808e9b6fb	Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair.	2017-05-14 22:08:15 -04:00
Thomas Harte	d1fe07f14d	Added test of perfect DPLL input timing.	2016-07-12 21:42:23 -04:00
Thomas Harte	d8334edf4a	Started trying to clean up, including commuting the C1540 source file name to match its class name but mainly by adding documentation.	2016-07-10 07:46:20 -04:00
Thomas Harte	66caa3c6dc	Fixed setup of bridge class.	2016-07-09 17:23:43 -04:00
Thomas Harte	bf03985ea4	Here's an instantly failing test...	2016-07-09 17:22:10 -04:00
Thomas Harte	865eb421cd	Quick on-disk tidy up.	2016-07-09 15:44:55 -04:00