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Commit Graph

127 Commits

Author SHA1 Message Date
Thomas Harte
bbb17acf3a Expanded interface so that an external machine caller can request a string be typed without any knowledge of whatever it intends to do re: CharacterMappers. Which is immediately useful in paste functionality. 2017-08-03 11:50:50 -04:00
Thomas Harte
ad3a98387f Within the Typer framework: hatched out CharacterMapper as a distinct thing from the target for keypresses, better to formalise responsibility but also to make it easy cleanly to sever that stuff into its own little part. 2017-08-03 11:42:31 -04:00
Thomas Harte
2f2071be8a These should actually both be in the public header, as the types are used in an exposed method. 2017-08-02 22:18:30 -04:00
Thomas Harte
6d510e4e70 Made it no longer public knowledge that any sort of Typer is involved in being a ZX80/81. 2017-08-02 22:17:22 -04:00
Thomas Harte
8e0736fbe6 Reinstated typing ability, albeit with an ugly inline insertion. But I think I can defer dealing with typers to another pull request. The whole issue of keyboard mapping probably needs reappraisal. 2017-08-02 22:16:09 -04:00
Thomas Harte
681d1e2f8d Breaking its typer for now, adapted the ZX80/81 to having a Z80, not being one. 2017-08-02 22:12:59 -04:00
Thomas Harte
4abd62e62b Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty. 2017-07-27 22:05:29 -04:00
Thomas Harte
968d2bb8ba Brought Typer into the new run_for orthodoxy, making it easier to clock consistently regardless of unit. Which necessitated adding a negative operator for WrappedInts. 2017-07-27 21:53:45 -04:00
Thomas Harte
8848ebbd4f Formalised set_interrupt_line's optional parameter as being a count of HalfCycles; corrected PartialMachineCycle.is_wait and effected the proper timing for counter reset on a ZX81. 2017-07-27 21:10:14 -04:00
Thomas Harte
8361756dc4 Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock. 2017-07-27 07:40:02 -04:00
Thomas Harte
81a3899381 Adjusted the Z80 formally to communicate in terms of half cycles rather than whole. 2017-07-26 19:42:00 -04:00
Thomas Harte
966b5e6372 Adapted the Z80's perform_machine_cycle to return Cycles. 2017-07-25 22:25:44 -04:00
Thomas Harte
8a2bdb8d22 Converted the TimedEventLoop and the things that sit atop it into ClockReceivers. 2017-07-24 21:19:05 -04:00
Thomas Harte
b82bef95f3 Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion. 2017-07-24 20:10:05 -04:00
Thomas Harte
ba088e5545 Adapted the Z80 into a clock receiver, which also vends Cycles rather than a raw int within its PartialMachineCycle struct. The objective is to update it to vend HalfCycles within its struct, but I think I need to do some work on cycle/half-cycle arithmetic first. 2017-07-23 22:15:04 -04:00
Thomas Harte
c2a7dffa7d Converted the ZX80/81 video component into a ClockReceiver. As it happens, it's most convenient to take the half-cycle bus here. 2017-07-22 23:02:28 -04:00
Thomas Harte
2ff157cf7a Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that. 2017-07-22 22:17:29 -04:00
Thomas Harte
a3e0024980 Chopped time accumulation out of the default Tape process because it's proving to be sufficiently expensive for a TZX as not to be worthwhile. Introduced a cheaper position capturing/restoring method. 2017-07-21 18:55:03 -04:00
Thomas Harte
44e5a03cf2 Removed just-don't-power-the-tape approach to pausing and playing, in favour of being fully communicative. 2017-07-19 19:21:27 -04:00
Thomas Harte
ac59dd8b1d Added enough typing to issue a load command. No thoughts as to running yet though. 2017-07-09 22:07:12 -04:00
Thomas Harte
3e5c209039 Added basic Typer support for the ZX80 and '81. 2017-07-09 22:00:34 -04:00
Thomas Harte
87658e83c1 Moved line counter reset logic; I think this is actually correct. 2017-07-09 00:05:30 -04:00
Thomas Harte
4509c3ce34 By observation, it appears that disabling vsync occurs on any port output whatsoever, as long as NMI isn't blocking it. 2017-07-08 21:01:52 -04:00
Thomas Harte
d6b87053bf Introduced an explicit record of whether a video byte is latched. It's definitely incorrect to treat the latching of 0 as equivalent to no latching, as the byte that will eventually become video is not strongly implied. 2017-07-08 20:40:19 -04:00
Thomas Harte
22389a5d2d Merge branch 'master' into HiRes 2017-07-08 20:38:25 -04:00
Thomas Harte
54efcb7e2f Made a game attempt at automatic motor control and ensured setting is initialised correctly from the user defaults. 2017-07-08 19:31:20 -04:00
Thomas Harte
e2575d6de4 Routed tape motor selections through to the C++ side of the world, and ensured that manual tape playback works properly. 2017-07-08 19:21:12 -04:00
Thomas Harte
46fff8e8a2 Ensured bit 8 is uniquely from the latched video byte, not an OR of that with the refresh address. 2017-07-06 22:48:48 -04:00
Thomas Harte
a3684545b5 Added a block on the tape motor for a short period after each time the ROM routine is intercepted for a substituted byte read. To reduce the collision between fast tape and real tape loading. 2017-07-06 22:33:54 -04:00
Thomas Harte
a72a2e0a1a Ensured tape doesn't proceed of its own volition when in fast-loading mode. 2017-06-23 20:21:37 -04:00
Thomas Harte
50375fb373 Ensured tape position is unaffected if the attempt at loading quickly fails. 2017-06-23 20:18:19 -04:00
Thomas Harte
cb105fdeb4 Took a first stab at high-res support. 2017-06-22 22:48:17 -04:00
Thomas Harte
acfd4dde36 Reduced port writes which can adjust programmatic sync, and prevented anything while NMI generation is active. Moved line counter increment from triggered by interrupt acknowledge to triggered by horizontal sync. In both cases, cribbing from my own earlier work. Initial results suggest that sync issues are resolved in third-party software. 2017-06-22 22:44:06 -04:00
Thomas Harte
644ef13acd Connected up the fast-tape GUI option for the ZX80 and '81. 2017-06-22 20:20:31 -04:00
Thomas Harte
b7c978e078 Added getters for most of the input lines, and attempted to round out the ZX81's wait logic. 2017-06-22 20:11:19 -04:00
Thomas Harte
52d9ddf9e5 Gave the binary tape player a more logical assignment of wave level to output level. Which miraculously appears to have been the issue with the ZX80/81 tape loading — the inconsistency of silences seems to have been the issue. 2017-06-21 22:13:24 -04:00
Thomas Harte
a6810fc3ef Removed some minor duplicity and ensured that hsync/NMI ends on the nominated cycle, not one afterwards. 2017-06-21 21:44:42 -04:00
Thomas Harte
15f6c51062 Added the most trivial implementation of the ZX81 wait line. 2017-06-21 21:28:14 -04:00
Thomas Harte
e1355d4b62 Restored proper video output. 2017-06-21 21:18:09 -04:00
Thomas Harte
4bf13610ce Reinstated interrupts by moving the refresh test back into the refresh cycle. 2017-06-21 21:03:39 -04:00
Thomas Harte
0e0ce379b4 Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle. 2017-06-21 20:38:08 -04:00
Thomas Harte
36e8a11505 Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line. 2017-06-21 20:32:08 -04:00
Thomas Harte
e1a2580b2a Renamed BusOperation to MachineCycle::Operation. 2017-06-17 21:53:45 -04:00
Thomas Harte
08a542a324 Reenabled the fast-loading hack. 2017-06-15 18:30:12 -04:00
Thomas Harte
9b3d05e05f Simplified decoding logic. 2017-06-14 22:24:44 -04:00
Thomas Harte
d8e3103a2b Fixes: switched ZX80 and ZX81 timing to the correct way around, ensured that my wait takes effect if HALT **isn't** set, and made sure to recover from it. 2017-06-13 21:48:17 -04:00
Thomas Harte
76a64d13a0 Made a first attempt at ZX81 emulation. 2017-06-13 21:25:55 -04:00
Thomas Harte
1e975859c2 Started splitting ZX80 and ZX81 paths. Also the '80 fires its horizontal sync a little earlier than the '81, so pulled that back a little. 2017-06-13 20:09:09 -04:00
Thomas Harte
4c5261bfa0 Made first attempt to use the horizontal counter for something; here for sync timing only, even though I've gone exclusively with '81-style timing for now. 2017-06-12 22:28:30 -04:00
Thomas Harte
8b09b4180b This now at least remembers whether it is meant to be a ZX81 and has storage for a horizontal counter. 2017-06-12 21:33:16 -04:00
Thomas Harte
302c2e94de Corrected lingering hard-coded mask. So titles for memory configurations above 1kb now load. 2017-06-11 21:27:46 -04:00
Thomas Harte
06fe07932a While tidying up, killed an unused instance variable. 2017-06-11 21:21:26 -04:00
Thomas Harte
6913c7a018 This also can just use rom_mask_. 2017-06-11 19:29:20 -04:00
Thomas Harte
6b602c74b7 Made an attempt to support memory maps other than the unexpanded default of 1kb. 2017-06-11 19:29:02 -04:00
Thomas Harte
e40d553045 Bumped the tape parser up into the machine to ensure a maintained state. Temporarily disabled normally-timed tape playback. 2017-06-11 18:31:43 -04:00
Thomas Harte
e5b30cdfbb Attempted to ensure appropriate resumption of processing after quick-reading a tape byte. 2017-06-11 17:28:47 -04:00
Thomas Harte
84d2feb2e6 Cleaned up and implemented fast-tape hack. I've decided it'd be better to test some other software, potentially to give multiple issues to think about, rather than sitting around with just the one. 2017-06-11 16:42:49 -04:00
Thomas Harte
d910a4fd38 Adjusted to signal an interrupt during the refresh cycle rather than weirdly just afterwards. Which cuts video timing down by 4 cycles a line. There still might be a problem here somewhere though, as I'm getting 206 cycles/line and the internet states it should be 207.
Also: lots of printfs have grown temporarily as I try to figure out what I'm doing so wrong as to break loading.
2017-06-11 13:32:20 -04:00
Thomas Harte
5626d35bc4 Tried flipping the bit meaning; decided at least to leave it in full-byte form. 2017-06-06 18:38:05 -04:00
Thomas Harte
63e0802f4e Ensured tape input appears on the returned value. 2017-06-06 18:16:27 -04:00
Thomas Harte
8c66e1d99d Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data. 2017-06-06 17:53:23 -04:00
Thomas Harte
ca9e8aecd6 Made a seemingly unsuccessful attempt to add tape input. 2017-06-06 10:13:32 -04:00
Thomas Harte
cc4cb45e9d Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court. 2017-06-06 09:25:18 -04:00
Thomas Harte
ebbf6e6133 Surprisingly, I think this may actually be the correct output: stopped throwing away the I part of the refresh register and flipped black and white. 2017-06-06 09:03:09 -04:00
Thomas Harte
cba07dec7e Doubled up to display all eight pixels. To confirm that they are the wrong pixels. 2017-06-06 08:59:00 -04:00
Thomas Harte
6f7037b2b1 Made an initial stab at outputting half the correct pixels. 2017-06-06 08:55:07 -04:00
Thomas Harte
ef4b2f963d Probably more-or-less corrected. But this is all a bit too interdependent. 2017-06-05 23:52:56 -04:00
Thomas Harte
97f3ff03b6 Restored white background and attempted to correct output timing deficiencies. Incomplete success. 2017-06-05 23:50:04 -04:00
Thomas Harte
2fbc7a2869 Made a very basic attempt at getting something that at least demarcates proper graphics output. 2017-06-05 23:32:49 -04:00
Thomas Harte
4983718df7 Got to outputting something to the CRT. Should be just proper syncs and a paper background. It's not synchronising properly, so something is amiss in my timing. 2017-06-05 10:47:42 -04:00
Thomas Harte
23ca00fd9a Added memory fuzzing as a way to verify state being written by the Z80. Eventually discovered the HALT problem as fixed in the last commit, so have stripped away the caveman stuff again. 2017-06-05 10:36:07 -04:00
Thomas Harte
893f61b490 Attempted specifically to reproduce the 1kb ZX80 memory map in the hope of getting compact lines and in case mirroring is why I'm getting completely empty video reads. Still no action. 2017-06-05 09:38:49 -04:00
Thomas Harte
7e3a46c33e [Re]discovered that sync may also be a product of the interrupt cycle. So started looking into that. 2017-06-04 21:54:55 -04:00
Thomas Harte
73654d51dd Wired up actually to run. 2017-06-04 18:37:13 -04:00
Thomas Harte
096551ab3e Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see. 2017-06-04 18:32:23 -04:00
Thomas Harte
c485c460f7 Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world. 2017-06-04 18:08:35 -04:00
Thomas Harte
d2637123c4 Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software. 2017-06-04 17:55:19 -04:00