Logo
Explore Mirrors Help
Sign In
6502/CLK
Watch 1
Star 0 Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2026-10-24 18:02:22 +00:00
Code Issues Projects Releases Wiki Activity
14,024 Commits 6 Branches 152 Tags
2fb3787267e7b2265b4e185ebca869284ae5909f
Commit Graph
9 Commits
Author SHA1 Message Date
Thomas Harte d177549dd6 Reduce more indentation. 2025-08-29 23:56:35 -04:00
Thomas Harte 2c2216afae Further eliminate file-relative includes. 2025-02-28 13:18:48 -05:00
Thomas Harte 3addb8d72b Finish updating components. 2024-11-30 17:21:00 -05:00
Thomas Harte a3d37640aa Switch include guards to #pragma once. 2024-01-16 23:34:46 -05:00
Thomas Harte 941d9a46a2 Makes a better effort at exposition; better implements clocked line. 2021-11-07 05:18:40 -08:00
Thomas Harte ecfe68d70f Introduce the principle that a Serial::Line can be two-wire — clock + data. 2021-11-06 16:54:20 -07:00
Thomas Harte f102d8a4b4 Extend to allow full-[byte/word/dword] writes, in LSB or MSB order. 2021-11-06 12:01:32 -07:00
Thomas Harte 25996ce180 Further doubles down on construction syntax for type conversions. 2020-05-09 23:00:39 -04:00
Thomas Harte e3abbc9966 Renames what didn't end up being a whole SerialPort. 2019-11-09 15:21:51 -05:00
Powered by Gitea Version: 28.2.0 Page: 286ms Template: 28ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API