2742 Commits

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Author	SHA1	Message	Date
Thomas Harte	cb732e5d5f	Made an attempt to wire in an [unclocked] AY, in an endeavour to get to keyboard reading.	2017-08-01 17:01:58 -04:00
Thomas Harte	2d4e202be3	Completed dangling comment.	2017-08-01 17:01:36 -04:00
Thomas Harte	64da8e17d1	Fixed: of course this should take a reference to an existing port handler rather than hatching its own; otherwise additional communication with a port handler by an i8255 owner doesn't work as intended.	2017-08-01 17:01:20 -04:00
Thomas Harte	08ad35efd9	It's barely an implementation of the 8255, but ensured that data is bounced into the PortHandler, conveniently assuming the interaction mode used by the CPC.	2017-08-01 16:34:13 -04:00
Thomas Harte	58b98267fc	Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.	2017-08-01 16:15:19 -04:00
Thomas Harte	ace71280a0	Removed implementation file; this is only ever going to be a template.	2017-08-01 16:00:17 -04:00
Thomas Harte	a27946102a	Took a shot at the interrupt counter. Attempts at keyboard reading now recur so it'll probably do for now. I think that next puts me into the realm of needing to implement the 8255.	2017-08-01 15:49:16 -04:00
Thomas Harte	1d99c116e7	Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.	2017-08-01 15:29:37 -04:00
Thomas Harte	ee27e16fb1	Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.	2017-08-01 15:19:25 -04:00
Thomas Harte	6ac7132799	Had a quick go at properly outputting Mode 1, adding wiring to communicate palette and mode changes to the CRTC bus handler. Colours are off but it's sufficient for now.	2017-08-01 15:16:13 -04:00
Thomas Harte	ca42abab70	Doubled up to ensure that every byte that should be inspected is represented. This makes it clearer that I'm on the right road. A garbled version of 'Amstrad 64k Microcomputer' can be discerned, in a weird grayscale and with the right-hand column missing and skewed output as a result.	2017-08-01 07:56:44 -04:00
Thomas Harte	933d69a256	Fixed slightly: the CPC wiki has a typo. It's 12 and 13 that move up to 14 and 15.	2017-08-01 07:51:13 -04:00
Thomas Harte	3b1db14817	Made a quick attempt at properly updating the refresh address.	2017-08-01 07:36:03 -04:00
Thomas Harte	10a5581aea	Made first attempt at offering some sort of pictographic of actual RAM contents.	2017-08-01 07:34:12 -04:00
Thomas Harte	3ae699964f	Ensured an actual pixel stream is supplied for pixel regions. Though it's just a long stream of white pixels for now. So visual output is unchanged.	2017-08-01 07:24:29 -04:00
Thomas Harte	9d953421d8	After a quick check, added a couple of other _delegate initialisations. I should probably find a way to template this.	2017-08-01 07:07:43 -04:00
Thomas Harte	763e3b65d1	Ensured a proper initial value for delegate_.	2017-07-31 22:46:06 -04:00
Thomas Harte	42dd27c9b1	Shunted method bodies inline, given that there's no need for a declaration/definition distinction.	2017-07-31 22:39:25 -04:00
Thomas Harte	2b168f7383	Disabled the address sanitiser as an every-time run again, as it just pushes my computer a bit too far.	2017-07-31 22:32:56 -04:00
Thomas Harte	0536f089e1	Eliminated old-[personal-]fashioned line break.	2017-07-31 22:32:26 -04:00
Thomas Harte	3df13cddd4	As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details.	2017-07-31 22:32:04 -04:00
Thomas Harte	e3f677fa37	I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.	2017-07-31 22:21:46 -04:00
Thomas Harte	c2253c1e0f	Fixed multiplier: the dot clock I've used to instantiate the CRT is the pixel clock, not the character clock.	2017-07-31 22:17:46 -04:00
Thomas Harte	5c68b6cc21	Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.	2017-07-31 22:16:08 -04:00
Thomas Harte	ffaa627820	Fixed frame restart when there is no adjustment period.	2017-07-31 22:13:45 -04:00
Thomas Harte	f742fd5d4a	Made basic attempt to get something on screen: white where the display is enabled, black for the border.	2017-07-31 22:13:20 -04:00
Thomas Harte	69b99fe127	Transferred ownership of the CRT to the CRTC bus handler, to give it easy access.	2017-07-31 22:04:52 -04:00
Thomas Harte	5a396f6787	Added an explicit cast.	2017-07-31 22:04:31 -04:00
Thomas Harte	cb0dc7b434	I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.	2017-07-31 22:01:54 -04:00
Thomas Harte	e28829bd1b	Corrected CRTC timing, gave it someone to talk to and a means with which to talk.	2017-07-31 20:14:46 -04:00
Thomas Harte	68ceeab610	Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.	2017-07-31 19:56:59 -04:00
Thomas Harte	68dca9d047	Made a first attempt at ROM paging, with pretty much the same scheme that'll be needed for 128kb support.	2017-07-31 19:37:28 -04:00
Thomas Harte	d88ca151f4	Added a first attempt at output port decoding. Just logging for now.	2017-07-31 19:25:10 -04:00
Thomas Harte	3c90218c3d	With a very basic stab at something a bit like the memory map (sans paging), execution begins.	2017-07-31 19:15:43 -04:00
Thomas Harte	afd409c883	Ensured that ROM images are loaded and passed to the Amstrad CPC.	2017-07-31 18:44:49 -04:00
Thomas Harte	26b6c03a2a	Re-enabled the address sanitiser as a development tool.	2017-07-31 07:30:07 -04:00
Thomas Harte	9c04d851e4	Added the basics necessary to get the CPU ticking over, at a nominal 4Mhz but with the wait states that I currently believe to be accurate.	2017-07-31 07:29:50 -04:00
Thomas Harte	1d6fe11906	Added an instance of Outputs::CRT::CRT. So progress is now: select CDT, up comes a blank window.	2017-07-31 07:16:51 -04:00
Thomas Harte	c0f1313830	Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.	2017-07-30 22:05:29 -04:00
Thomas Harte	fb51fadf00	Merge branch 'master' into CPC	2017-07-30 21:29:31 -04:00
Thomas Harte	55fd9122d0	Slightly relaxed vertical sync testing.	2017-07-30 21:19:42 -04:00
Thomas Harte	5b5720fac0	Added to the static analyser the most basic through-path for Amstrad CPC content.	2017-07-30 21:15:20 -04:00
Thomas Harte	d25d7d7d40	Added the Amstrad CPC as a named target and declared support for its CDT file format.	2017-07-29 21:56:33 -04:00
Thomas Harte	ba4f2d8917	Merge branch 'master' into VerticalSync	2017-07-29 21:45:22 -04:00
Thomas Harte	a2aec39633	Merge pull request #167 from TomHarte/VerticalSync ... Adjusts vertical sync detection	2017-07-29 21:44:47 -04:00
Thomas Harte	0bf4fdc9af	Simplified slightly.	2017-07-29 21:37:59 -04:00
Thomas Harte	ed8c73eb14	Ensured lengthy constant sync can't appear to be two sync pulses, regardless of other interruption.	2017-07-29 18:25:04 -04:00
Thomas Harte	3528a7f78b	Made an attempt at triggering vertical sync the expected number of time after it begins, regardless of total length.	2017-07-29 17:33:52 -04:00
Thomas Harte	54bcc40192	With an eye towards being more accurate as to vertical sync recognition: acknowledged that the detection period varies between PAL and NTSC.	2017-07-29 14:53:53 -04:00
Thomas Harte	4b5e9ffb83	Ensured is_at_end_ is initially cleared by default.	2017-07-27 22:22:43 -04:00