Thomas Harte
3a02c22072
Provide an always-16bit-address route to the stack.
2023-07-30 16:25:51 -04:00
Thomas Harte
28c79b2885
Eliminate redundant [space][tab] pairs.
2023-05-12 14:14:45 -04:00
Thomas Harte
45dc99fb9d
Further improve exposition.
2022-09-09 15:48:25 -04:00
Thomas Harte
4467eb1c41
Ensure relevant throwaway stack reads use the previous stack address.
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TODO: can CycleFetchPreviousThrowaway be used more widely?
2022-06-24 14:00:03 -04:00
Thomas Harte
7dcfa9eb65
65816: improve decimal calculations, posted IO addresses, read/write during redundant read-modify-write cycle.
2022-06-21 14:33:06 -04:00
Thomas Harte
ec98736bd7
Ensure IO cycles don't produce an address of (PC+1).
2022-06-21 11:41:05 -04:00
Thomas Harte
83d0cfc24e
Improves commentary.
2021-03-03 20:33:28 -05:00
Thomas Harte
72d7901c88
Takes a shot at the keyboard data full flag.
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Just a guess. But likely?
2021-02-19 20:06:12 -05:00
Thomas Harte
574a37814c
Attempts to fix exception selection and timing.
2020-12-08 18:46:30 -05:00
Thomas Harte
d3c7253981
Shifts size-limiting of X and Y to transitions and mutations, away from reads.
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Primarily to remove potential bug-causing complexity — this is easier to debug. But let's see.
2020-11-04 20:35:41 -05:00
Thomas Harte
5cbb91f352
Fixes COP vector, ensures WDM skips a byte.
2020-11-03 20:01:02 -05:00
Thomas Harte
e8943618dc
Adds some extra commentary and distinguishes X/Y sizing from M.
2020-10-31 10:21:13 -04:00
Thomas Harte
1df2ce513a
Ensures that reset doesn't push to the stack.
2020-10-28 21:23:35 -04:00
Thomas Harte
1e4679ae14
Corrects JSL and RTL.
2020-10-28 17:25:40 -04:00
Thomas Harte
99eba2f8ba
Ensures intended 65816 exception behaviour.
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i.e. the relevant micro-op sequence exists, and its operation isn't lost. Also sets the 65816 by default to jump straight into power-on, not to execute an instruction first. That shouldn't make a functional difference, but it makes debugging easier because it makes startup fully deterministic.
2020-10-18 14:43:47 -04:00
Thomas Harte
3b398f7a9a
Attempts to complete all 65816 bus signalling.
2020-10-16 21:56:20 -04:00
Thomas Harte
096add7551
Exposes non-BusOperation bus outputs.
2020-10-16 21:05:42 -04:00
Thomas Harte
68c15bd605
Updates Qt project; catches another couple of issues via its compiler.
2020-10-15 21:09:22 -04:00
Thomas Harte
c0a1c34012
Wraps all registers into a struct, so that I can implement abort.
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Makes some preparations for ready too.
2020-10-15 18:42:38 -04:00
Thomas Harte
3c6adc1ff4
Completes 65816 addressing mode tests and corresponding fixes.
2020-10-14 22:00:52 -04:00
Thomas Harte
27afb8f0a7
Adds direct indirect long test, and thereby fixes addressing mode.
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Nine to go!
2020-10-14 21:26:20 -04:00
Thomas Harte
b22aa5d699
Starts transcribing the addressing examples I have into tests.
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Correspondingly extends the exposed register set and test-machine addressing range.
2020-10-13 21:38:30 -04:00
Thomas Harte
8f5537aaaa
Attempts to resolve my direct-indirect addressing stumble.
2020-10-13 20:21:53 -04:00
Thomas Harte
a15d4a156b
Starts trying to ensure appropriate address wrapping.
2020-10-12 22:33:43 -04:00
Thomas Harte
f529eadbec
Corrects 16-bit read-modify-write.
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Subject to the TODO proviso on 'correct'; has my 6502 prejudice pushed me into unrealistic bus signalling?
2020-10-12 18:36:09 -04:00
Thomas Harte
5dc3cd3a2f
Starts using Jeek816 for a basic native-mode audit. Fixes absolute long addressing.
2020-10-11 22:02:46 -04:00
Thomas Harte
82797fd395
Attempts to do the proper thing for interrupts.
2020-10-11 21:10:44 -04:00
Thomas Harte
a0885ab7d0
Implements STP and WAI.
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Albeit still without fully-implemented reactions to exceptions in general.
2020-10-11 17:56:55 -04:00
Thomas Harte
8eaf1303a3
Attempts proactively to ensure proper RTI behaviour on the 65816.
2020-10-11 15:25:13 -04:00
Thomas Harte
071ad6b767
I don't think RTL is needed; JML looks like it covers it.
2020-10-10 22:16:35 -04:00
Thomas Harte
ae87728770
Ensures M and X are exposed to the public interface.
2020-10-10 21:33:56 -04:00
Thomas Harte
28c8ba70c1
Implements REP and SEP and exposes the MX flags generally.
2020-10-10 21:23:59 -04:00
Thomas Harte
451f83ba51
Corrects emulation-mode read-modify-writes not to empty the data buffer.
2020-10-09 22:14:42 -04:00
Thomas Harte
0ed98cbfac
Attempts to fix direct indirect indexed; not yet successful I think.
2020-10-08 22:15:19 -04:00
Thomas Harte
7dde7cc743
Implements altered direct indexed addressing in emulation mode.
2020-10-08 22:02:14 -04:00
Thomas Harte
0418f51ef2
Takes a shot at emulation-mode 'exceptions'.
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It's just RTI and correct decimal SBC left of the official 6502s now, I think.
2020-10-08 17:52:13 -04:00
Thomas Harte
054e0af071
Corrects RTS behaviour: the return address on the stack is off by one.
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Dormann's tests now proceed to a BRK.
2020-10-08 16:55:45 -04:00
Thomas Harte
907c3374c3
Attempts to clean up my JMP/JSR mess.
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Also takes a step forwards in decimal SBC, but it's not right yet.
2020-10-08 16:48:46 -04:00
Thomas Harte
b608e11965
Realises that not all non-incrementing PC fetches should be thrown away.
2020-10-07 20:06:27 -04:00
Thomas Harte
7439a326a6
Implements BIT (in regular and immediate forms).
2020-10-07 18:15:18 -04:00
Thomas Harte
7065ba4857
Implements the single-byte branches.
2020-10-06 21:24:43 -04:00
Thomas Harte
9ce9167e3c
Formalises work left to do.
2020-10-06 19:12:19 -04:00
Thomas Harte
993eff1d3d
Starts slowly, with flag manipulation.
2020-10-06 16:25:30 -04:00
Thomas Harte
b7ba0d4327
Attempts to complete all addressing modes.
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So, if bugs didn't exist, it'd just be members of the Operation enum to go.
2020-10-05 17:04:57 -04:00
Thomas Harte
d8dccf2500
Attempts a full implementation of MVN and MVP.
2020-10-04 19:21:04 -04:00
Thomas Harte
4ebf594b3b
This should bring me up to absolute, y.
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i.e. next is datasheet program 7.
2020-10-04 19:02:47 -04:00
Thomas Harte
8a83024962
Starts a dash towards just completing the addressing modes for now.
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This brings me up to the end of absolute long (i.e. 4a on the datasheet).
2020-10-04 18:52:46 -04:00
Thomas Harte
bdc1136b96
Edges towards working short absolute addressing mode.
2020-10-03 21:30:24 -04:00
Thomas Harte
b83d93abc2
Accepts that whether instructions do 8- or 16-bit bus accesses depends on either M or X depending on the operation.
2020-10-02 17:08:30 -04:00
Thomas Harte
78b3ec4b10
The actual work begins: starts implementing 65816 micro-ops.
2020-09-29 18:42:07 -04:00
