1
0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-30 04:50:08 +00:00
Commit Graph

68 Commits

Author SHA1 Message Date
Thomas Harte
ca42abab70 Doubled up to ensure that every byte that should be inspected is represented. This makes it clearer that I'm on the right road. A garbled version of 'Amstrad 64k Microcomputer' can be discerned, in a weird grayscale and with the right-hand column missing and skewed output as a result. 2017-08-01 07:56:44 -04:00
Thomas Harte
933d69a256 Fixed slightly: the CPC wiki has a typo. It's 12 and 13 that move up to 14 and 15. 2017-08-01 07:51:13 -04:00
Thomas Harte
10a5581aea Made first attempt at offering some sort of pictographic of actual RAM contents. 2017-08-01 07:34:12 -04:00
Thomas Harte
3ae699964f Ensured an actual pixel stream is supplied for pixel regions. Though it's just a long stream of white pixels for now. So visual output is unchanged. 2017-08-01 07:24:29 -04:00
Thomas Harte
42dd27c9b1 Shunted method bodies inline, given that there's no need for a declaration/definition distinction. 2017-07-31 22:39:25 -04:00
Thomas Harte
3df13cddd4 As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details. 2017-07-31 22:32:04 -04:00
Thomas Harte
c2253c1e0f Fixed multiplier: the dot clock I've used to instantiate the CRT is the pixel clock, not the character clock. 2017-07-31 22:17:46 -04:00
Thomas Harte
f742fd5d4a Made basic attempt to get something on screen: white where the display is enabled, black for the border. 2017-07-31 22:13:20 -04:00
Thomas Harte
69b99fe127 Transferred ownership of the CRT to the CRTC bus handler, to give it easy access. 2017-07-31 22:04:52 -04:00
Thomas Harte
e28829bd1b Corrected CRTC timing, gave it someone to talk to and a means with which to talk. 2017-07-31 20:14:46 -04:00
Thomas Harte
68ceeab610 Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation. 2017-07-31 19:56:59 -04:00
Thomas Harte
68dca9d047 Made a first attempt at ROM paging, with pretty much the same scheme that'll be needed for 128kb support. 2017-07-31 19:37:28 -04:00
Thomas Harte
d88ca151f4 Added a first attempt at output port decoding. Just logging for now. 2017-07-31 19:25:10 -04:00
Thomas Harte
3c90218c3d With a very basic stab at something a bit like the memory map (sans paging), execution begins. 2017-07-31 19:15:43 -04:00
Thomas Harte
afd409c883 Ensured that ROM images are loaded and passed to the Amstrad CPC. 2017-07-31 18:44:49 -04:00
Thomas Harte
9c04d851e4 Added the basics necessary to get the CPU ticking over, at a nominal 4Mhz but with the wait states that I currently believe to be accurate. 2017-07-31 07:29:50 -04:00
Thomas Harte
1d6fe11906 Added an instance of Outputs::CRT::CRT. So progress is now: select CDT, up comes a blank window. 2017-07-31 07:16:51 -04:00
Thomas Harte
c0f1313830 Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT. 2017-07-30 22:05:29 -04:00