Thomas Harte
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43fcf46d69
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Limit line lengths.
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2024-12-01 09:00:29 -05:00 |
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Thomas Harte
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a7d2b0f63b
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Const as many arguments as possible.
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2024-10-13 21:40:39 -04:00 |
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Thomas Harte
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a3d37640aa
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Switch include guards to #pragma once .
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2024-01-16 23:34:46 -05:00 |
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Thomas Harte
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de230fb6be
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Resolve for work factored out.
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2023-10-25 22:21:23 -04:00 |
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Thomas Harte
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28c79b2885
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Eliminate redundant [space][tab] pairs.
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2023-05-12 14:14:45 -04:00 |
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Thomas Harte
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2b56b7be0d
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Simplify namespace syntax.
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2023-05-10 16:02:18 -05:00 |
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Thomas Harte
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9a56d053f8
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Introduce/extend 68k enums to cover 68020 instruction set.
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2022-10-22 15:20:30 -04:00 |
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Thomas Harte
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ec728ad573
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Fix ADD/SUBX carry.
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2022-10-19 22:17:51 -04:00 |
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Thomas Harte
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bc9ddacb8d
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Improve commentary.
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2022-10-19 14:40:29 -04:00 |
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Thomas Harte
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979bf42541
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Fix ASL overflow test.
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2022-10-18 22:43:17 -04:00 |
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Thomas Harte
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d09473b66f
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Move common negative and zero logic into Status.
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2022-10-18 14:51:51 -04:00 |
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Thomas Harte
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b31b4a5d10
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Reformulate NOT in terms of EOR, and clean up elsewhere.
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2022-10-18 12:17:55 -04:00 |
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Thomas Harte
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5560a0ed39
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Fix overflow test for ASL.
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2022-10-18 11:47:36 -04:00 |
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Thomas Harte
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a1ae7c28b2
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Add various insurances against undefined behaviour.
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2022-10-18 11:30:40 -04:00 |
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Thomas Harte
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fb2b7969a2
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Add TODO to self on undefined behaviour.
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2022-10-17 23:14:14 -04:00 |
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Thomas Harte
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abb19e6670
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Populate carry whenever count != 0, regardless of modulo.
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2022-10-17 22:57:21 -04:00 |
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Thomas Harte
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555250dbd9
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Don't trample on X before use.
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2022-10-17 22:19:35 -04:00 |
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Thomas Harte
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8148397f62
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Fill in comments, eliminate u/s_extend16 macros.
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2022-10-17 15:37:13 -04:00 |
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Thomas Harte
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f095bba1ca
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Eliminate bitwise macros.
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2022-10-17 15:21:54 -04:00 |
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Thomas Harte
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ee3a3df0b5
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Eliminate SBCD macro.
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2022-10-17 15:12:38 -04:00 |
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Thomas Harte
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aff1caed15
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Clean up formatting.
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2022-10-17 15:05:23 -04:00 |
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Thomas Harte
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da03cd58c1
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Add overt casting.
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2022-10-17 15:04:28 -04:00 |
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Thomas Harte
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ce98ca4bdd
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Pull RO[L/R][X]m out of their macro stupor.
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2022-10-17 11:27:04 -04:00 |
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Thomas Harte
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cc55f0586d
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Clean up ASL/ASR/LSL/LSRm.
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2022-10-17 11:18:10 -04:00 |
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Thomas Harte
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47e8f3c0f1
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Collapse [A/L]S[L/R].[bwl] into a template.
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2022-10-16 22:21:20 -04:00 |
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Thomas Harte
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d5ceb934d2
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Fix overflow flags, avoid bigger-word usage.
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2022-10-16 21:52:00 -04:00 |
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Thomas Harte
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17c1e51231
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Commute ROL/ROR to templates.
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2022-10-16 12:19:09 -04:00 |
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Thomas Harte
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fee072b404
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Commute ROXL and ROXR into a template.
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2022-10-16 12:06:28 -04:00 |
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Thomas Harte
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0a9c392371
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Remove unused bit_count .
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2022-10-13 15:01:06 -04:00 |
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Thomas Harte
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06dbb7167b
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Unify TST.
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2022-10-11 21:31:14 -04:00 |
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Thomas Harte
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eff9a09b9f
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Collapse MOVE and NEG[X] similarities.
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2022-10-11 21:27:18 -04:00 |
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Thomas Harte
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1f19141746
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Eliminate BiggerInt .
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2022-10-11 16:19:47 -04:00 |
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Thomas Harte
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28093196b9
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Convert DIVU/DIVS logic to a template.
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2022-10-11 16:16:53 -04:00 |
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Thomas Harte
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eb206a08d9
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Templatise MULU/MULS.
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2022-10-11 16:02:20 -04:00 |
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Thomas Harte
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b2f005da1b
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Collapse SR/CCR bitwise operations into a template.
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2022-10-11 15:53:11 -04:00 |
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Thomas Harte
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8305a3b46a
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Consolidate compare logic.
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2022-10-11 12:57:02 -04:00 |
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Thomas Harte
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f3f23f90a3
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Consolidate repetition in CLR.
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2022-10-11 11:22:34 -04:00 |
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Thomas Harte
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77bc60bf86
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Consolidate BCLR, BCHG and BSET into a macro.
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2022-10-11 10:47:55 -04:00 |
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Thomas Harte
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ec5d57fefe
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Eliminate 64-bit work.
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2022-10-11 10:33:28 -04:00 |
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Thomas Harte
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58396f0c52
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Perform a prima facie conversion of ADD/SUB[/X] from macros to templates.
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2022-10-10 22:21:13 -04:00 |
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Thomas Harte
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c3b436fe96
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Use int64_t as an intermediary to avoid x86 exception on INT_MIN/-1.
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2022-06-02 21:39:52 -04:00 |
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Thomas Harte
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659e4f6987
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Include fixed cost of rolls. Which includes providing slightly more information to did_shift .
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2022-06-01 20:30:51 -04:00 |
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Thomas Harte
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8ffaf1a8e4
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Ensure did_divu/s are performed even upon divide by zero.
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2022-05-29 21:18:19 -04:00 |
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Thomas Harte
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7788a109b0
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Tweak more overtly to avoid divide by zero.
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2022-05-29 20:51:50 -04:00 |
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Thomas Harte
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9e3c2b68d7
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Eliminate potential future implicit conversion warnings.
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2022-05-24 11:05:24 -04:00 |
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Thomas Harte
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cb77519af8
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Make BSR operate like the other offsets: the flow controller gets whatever was in the opcode.
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2022-05-20 12:40:09 -04:00 |
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Thomas Harte
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452dd3ccfd
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Add a performer call-out for Scc; use it to implement proper timing in the mk2 68000.
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2022-05-20 11:20:23 -04:00 |
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Thomas Harte
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acb63a1307
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Pull generalised DIVU/DIVS into a macro.
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2022-05-15 20:01:51 -04:00 |
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Thomas Harte
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341bf2e480
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Repattern DIVS after DIVU.
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2022-05-15 16:54:58 -04:00 |
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Thomas Harte
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f83954f5b7
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Switch to common bit-selection logic.
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2022-05-13 15:08:15 -04:00 |
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