9 Commits

Author	SHA1	Message	Date
Thomas Harte	48b0d8c329	Adds bus req/ack to the DMA controller; hacks support into the ST.	2019-11-03 21:11:25 -05:00
Thomas Harte	4dbd2a805a	Nudges closer to DMA support.	2019-11-03 17:24:36 -05:00
Thomas Harte	0567410bcf	Attempts to start getting the WDC working.	2019-11-02 23:26:42 -04:00
Thomas Harte	6d1e09ba55	Connects up the AY to floppy drive/side selection.	2019-11-02 23:04:08 -04:00
Thomas Harte	731dc350b4	Adds sometime real-time clocking for DMA.	2019-10-30 22:59:32 -04:00
Thomas Harte	0f2d72c436	Ensures receipt of output line changes.	2019-10-28 21:21:53 -04:00
Thomas Harte	95d3b6e79f	Adds a through route for the FDC interrupt line.	2019-10-28 21:13:21 -04:00
Thomas Harte	36a9a5288b	Adds drives to the FDC.	2019-10-26 22:39:11 -04:00
Thomas Harte	ac39fd0235	Starts work on the DMA controller.	2019-10-26 21:33:57 -04:00