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4,766 Commits 8 Branches 121 Tags 496 MiB
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172 Commits

Author SHA1 Message Date
Thomas Harte
ffdf02c5df Adds MOVE XXX.lw, -(An) 2019-04-18 23:40:54 -04:00
Thomas Harte
27c7d00a05 Commutes final missing MOVEs to TODOs. 2019-04-18 23:35:32 -04:00
Thomas Harte
64c4137e5b Begins a cleanup procedure on MOVE. 2019-04-18 23:25:19 -04:00
Thomas Harte
8c26d0c6e6 Makes an attempt at RTE and RTR. 2019-04-18 20:50:58 -04:00
Thomas Harte
81dcfd9f85 Implements AND, OR and EOR. 
As well as introducing a little more nuance to the double-decoding test.
 2019-04-18 16:34:48 -04:00
Thomas Harte
9334557fbf Added important TODO. 2019-04-17 23:12:32 -04:00
Thomas Harte
b09de8efce Attempts to fill in the rest of MOVE x, -(An). 2019-04-17 23:05:16 -04:00
Thomas Harte
5a50eb56dd Marginally increases coverage of MOVE x, -(An). 2019-04-17 22:30:07 -04:00
Thomas Harte
e49b257e94 Takes a run at TRAP. 2019-04-17 22:21:56 -04:00
Thomas Harte
b8a0f4e831 Implements MOVE to/from USP. 2019-04-17 16:58:59 -04:00
Thomas Harte
29f8dcfb40 Fixes a bunch of (d16, An)-type MOVEs and implements MOVE (XXX).wl, (d16,An)/etc. 2019-04-17 16:13:35 -04:00
Thomas Harte
0c05983617 Shortens impact of MULU on the instruction stream to correct parsing. 
I need to look into this.
 2019-04-17 15:15:48 -04:00
Thomas Harte
0bd653708c Corrects MOVE.bw Dn, (An)[+]. 2019-04-17 14:31:20 -04:00
Thomas Harte
41d800cb63 Fixes ADD/SUB Dn,x to use the proper destination value. 2019-04-17 10:23:47 -04:00
Thomas Harte
cadc0bd509 Mental delusion lifted: JSR doesn't look enough like BSR. 2019-04-17 10:02:14 -04:00
Thomas Harte
b64da2710a Corrects a few MOVE #s. 2019-04-17 10:00:14 -04:00
Thomas Harte
82b08d0e3a Corrects addressing behaviour of nRd[+-]. 2019-04-17 08:53:34 -04:00
Thomas Harte
8f77d1831b Implements MULU and MULS. 2019-04-16 22:16:43 -04:00
Thomas Harte
be722143e1 Completes addressing modes for ADDI/etc/etc. 2019-04-16 21:34:16 -04:00
Thomas Harte
d8d974e2d7 Consolidates JSR and BSR preparation. 2019-04-16 21:29:37 -04:00
Thomas Harte
9b7ca6f271 Implements the basics of EORI, ORI, ANDI, SUBI and ADDI. 
Also corrects the BSR return address.
 2019-04-16 19:50:10 -04:00
Thomas Harte
8ce018dbab Adds the necessary runtime support for AND, EOR and OR. 2019-04-16 15:17:40 -04:00
Thomas Harte
180062c58c Finishes fleshing out [ADD/SUB]Q. 2019-04-16 14:28:31 -04:00
Thomas Harte
37656f14d8 Adds basic addressing modes for [ADD/SUB]Q. 2019-04-16 11:19:45 -04:00
Thomas Harte
dec5535e54 Implements (arguably: fixes) BSR. 2019-04-15 23:20:36 -04:00
Thomas Harte
1f0e3b157a Corrects a couple of JSR and JMP addressing modes. 2019-04-15 22:37:11 -04:00
Thomas Harte
d802e83f49 Fills in further MOVEs. 2019-04-15 22:25:22 -04:00
Thomas Harte
ebcae25762 Adjusts JSR behaviour and further extends MOVE. 2019-04-15 22:02:52 -04:00
Thomas Harte
5330267d16 Implements BCLR. 2019-04-15 18:11:02 -04:00
Thomas Harte
892476973b Attempts RO{X}[L/R]. 2019-04-15 17:31:58 -04:00
Thomas Harte
84f4a25bc9 Completes TST. 2019-04-15 16:28:20 -04:00
Thomas Harte
1460a88bb3 Takes a run at JSR and RTS. 2019-04-15 15:14:38 -04:00
Thomas Harte
d25ab35d58 Finally gets setw usage correct. 2019-04-15 12:41:56 -04:00
Thomas Harte
a223cd90a1 Adds predecrement TSTs, increases QL running time, reduces logging. 2019-04-15 12:36:08 -04:00
Thomas Harte
aef92ba29c Corrects immediate shift count. 2019-04-15 12:25:45 -04:00
Thomas Harte
328d297490 Implements the first few addressing modes for TST. 2019-04-15 10:03:52 -04:00
Thomas Harte
3d240f3f18 Corrects decoding of DBcc. 2019-04-15 09:49:23 -04:00
Thomas Harte
45f35236a7 Corrects decoding of ADDA and SUBA. 2019-04-15 09:44:06 -04:00
Thomas Harte
fba210f7ce Corrects MOVE.l Dn, (An)[+]. 2019-04-15 09:30:49 -04:00
Thomas Harte
8a09e5fc16 Implements Scc. 2019-04-14 22:39:13 -04:00
Thomas Harte
75d8824e6b Eliminates implicit type conversion. 2019-04-14 21:02:28 -04:00
Thomas Harte
325af677d3 Implements MOVEM to M with an implicit type conversion. 2019-04-14 20:53:27 -04:00
Thomas Harte
1003e70b5e Implements MOVEM to R. 2019-04-14 20:02:18 -04:00
Thomas Harte
d70229201d Advances right up to the lack of MOVEM actions being the final piece. 2019-04-14 14:45:29 -04:00
Thomas Harte
823f91605b Still slow pedalling slightly, adds further MOVEM storage. 2019-04-14 14:31:13 -04:00
Thomas Harte
53f75034fc Commits at least to decoding MOVEM. 2019-04-14 14:09:28 -04:00
Thomas Harte
78649a5b54 Fleshes out MOVE, (XXX) a little further. 2019-04-12 17:16:03 -04:00
Thomas Harte
f48db625a0 Corrects write-back and zero flag for ADD/SUB.l. 2019-04-12 16:41:00 -04:00
Thomas Harte
2ba66c4457 Corrects MOVEA, adds extra test safeguards. 2019-04-12 16:10:17 -04:00
Thomas Harte
2c78ea1a4e Completes conversion away from magic constants. 2019-04-12 15:48:29 -04:00
Thomas Harte
73f50ac44e Commits further to elimination of magic constants. 2019-04-12 13:45:28 -04:00
Thomas Harte
9ce48953c1 Improves debugging printout. 2019-04-12 13:45:03 -04:00
Thomas Harte
1098cd0c6b Begins rooting out magic constants. 2019-04-11 22:31:17 -04:00
Thomas Harte
652ebd143c
Corrects addressing mode support for LEA. 2019-04-11 11:58:34 -04:00
Thomas Harte
8e9d7c0f40 Corrects register-relative address calculation. 2019-04-10 23:09:03 -04:00
Thomas Harte
a64948a2ba Permits zero-bus-op non-terminals. 2019-04-10 22:42:43 -04:00
Thomas Harte
43f619a081 Implements ASL, ASR, LSL and LSR. 2019-04-10 22:31:04 -04:00
Thomas Harte
a07de97df4 Implements the fixed part of register shifts. 2019-04-09 22:12:37 -04:00
Thomas Harte
85d25068a8 Attempts a full implementation of memory shifts. 2019-04-09 22:04:25 -04:00
Thomas Harte
7a0319cfe5 Kicks the work of dealing with ASL/etc into the runtime. 2019-04-09 21:48:08 -04:00
Thomas Harte
f750671f33 Stepping gingerly onwards, adds a double-decoding test. 
As a result of that, collapses BRA into Bcc. Which provisionally looks correct.
 2019-04-09 16:54:41 -04:00
Thomas Harte
7886fe677a Cleans up commenting. 2019-04-08 22:51:18 -04:00
Thomas Harte
73c027f8e3 Implements CMPA and CMPM. [Provisionally] completing the CMPs. 2019-04-08 22:40:38 -04:00
Thomas Harte
eda88cc462 Implements MOVE to CCR. 2019-04-07 22:24:17 -04:00
Thomas Harte
652f4ebfed Implements CLR, NEG, NEGX and NOT. 2019-04-07 22:07:39 -04:00
Thomas Harte
06a2f59bd0 Implements DBcc. 2019-04-06 23:21:01 -04:00
Thomas Harte
03f365e696 Corrects source/destination order of CMP setup. 2019-04-06 20:00:15 -04:00
Thomas Harte
49a22674ba Corrects MOVE destinations. 2019-04-06 18:33:53 -04:00
Thomas Harte
ec494511ec Implements CMP. 2019-04-06 10:41:19 -04:00
Thomas Harte
af02ce9c6e Attempts to correct various instances of PC-relative addressing. 2019-04-05 23:49:13 -04:00
Thomas Harte
56e42859ab Ensures the supervisor flag is updated properly on MOVE to SR. 2019-04-05 23:21:50 -04:00
Thomas Harte
2d153359f8 Adds BTST. 2019-04-04 21:43:22 -04:00
Thomas Harte
068ce23716 Adds a few more MOVEs. 2019-04-04 19:49:19 -04:00
Thomas Harte
03be2e3652 Adds decoding of ADDA and SUBA. 2019-04-03 22:39:01 -04:00
Thomas Harte
4ef2c0bed8 Completes ADD and SUB. 2019-04-03 21:41:59 -04:00
Thomas Harte
bfd405613c Reuse of addresses is also no longer implicit. 2019-04-03 21:27:11 -04:00
Thomas Harte
73e1c8c780 Corrects now-unimplemented ADD/SUB. 2019-04-03 19:43:54 -04:00
Thomas Harte
689ba1d4a2 Effective address adjustments now have to be explicit. 2019-04-03 19:13:10 -04:00
Thomas Harte
39b9d00550 Moves some way towards mapping out ADD and SUB, fixing a bug with address register modification. 2019-04-02 21:50:58 -04:00
Thomas Harte
64f99d83a4 Takes a stab at offering ADD, ADDA, SUB and SUBA operations. 
Not yet decoded.
 2019-04-01 21:21:26 -04:00
Thomas Harte
8f1faefa1c Implements further MOVEs and fixes a potential error in program formation. 2019-03-31 22:34:28 -04:00
Thomas Harte
a9ceef5c37 Improves communication slightly. 2019-03-31 22:27:33 -04:00
Thomas Harte
c6f977ed4b Corrects CMPI and documentation; implements JMP. 2019-03-31 21:13:26 -04:00
Thomas Harte
cb240cd32a Switches to a more explicit tokeniser, to allow for greater flexibility momentarily. 2019-03-30 23:11:39 -04:00
Thomas Harte
bc6349f823 Adds RESET, fixes branches and attempts to fix CMPI. 2019-03-29 23:40:54 -04:00
Thomas Harte
a93a1ae40f Completes MOVE.blw <ea>, Dn/An/(An)/(An)+, implements MOVEq. 2019-03-29 23:13:41 -04:00
Thomas Harte
25254255fe Implements a few additional MOVEs. 2019-03-27 21:26:04 -04:00
Thomas Harte
42634b500c Implements LEA. 2019-03-26 22:07:28 -04:00
Thomas Harte
be4b38c76a Adds BRA and Bcc. 2019-03-25 22:54:49 -04:00
Thomas Harte
7163b1132c Takes a run at CMPI. 
Also factors out a couple of mode things, clarifies on where things from the
prefetch are assembled to, and switches to ordering implemented instructions
alphabetically.
 2019-03-24 23:05:57 -04:00
Thomas Harte
3ccec1c996 Implements MOVE to SR, fleshing out the final bits of storage for the status word. 2019-03-24 18:20:54 -04:00
Thomas Harte
47359dc8f1 Adds tests for MOVE.l (An), Dn, and thereby correct their implementation. 2019-03-23 21:41:47 -04:00
Thomas Harte
43532c8455 Starts to make incursions into MOVE[A].l. 2019-03-23 21:03:52 -04:00
Thomas Harte
d7c3d4ce52 Adds test for MOVEA.w (0x1000), A1 and fixes implementation thereof. 2019-03-22 23:27:48 -04:00
Thomas Harte
ed7060a105 Made an initial stab at completing MOVEA.w. 
I think I'm probably peeking into the prefetch queue incorrectly.
 2019-03-22 21:43:51 -04:00
Thomas Harte
db0da4b741 Improves get/set state. 2019-03-22 19:34:17 -04:00
Thomas Harte
c9c16968bb Implements MOVEA as distinct from MOVE. 
At least as far as MOVE is implemented, that is.
 2019-03-22 19:25:53 -04:00
Thomas Harte
fdc598f2e1 Starts MOVE tests; in pursuit of which talks the 68000 into obeying run lengths. 2019-03-21 22:30:41 -04:00
Thomas Harte
f679145bd1 Makes a further push into the MOVEs. 
With some quick notation shortening.
 2019-03-20 23:21:02 -04:00
Thomas Harte
eeb161ec51 Converts the prefetch queue into a 32-bit quantity. 2019-03-19 21:33:52 -04:00