257 Commits

Author	SHA1	Message	Date
Thomas Harte	0e0ce379b4	Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.	2017-06-21 20:38:08 -04:00
Thomas Harte	36e8a11505	Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.	2017-06-21 20:32:08 -04:00
Thomas Harte	45f442ea63	Corrected interrupt mode 2: was both failing properly to load the vector address, and failing to read from it.	2017-06-21 19:08:48 -04:00
Thomas Harte	db743c90d8	Had neglected to count refresh time in my interrupt programs. Corrected. Mode 0 timing test succeeds again. Only Mode 2 is now at fault.	2017-06-21 18:58:44 -04:00
Thomas Harte	10cc94f581	Attempted to fix interrupt response timing; ensured initial interrupt mode is one that won't jump beyond the interrupt response program table's length, and that the conditionals other than CALL definitely have no alternative program attached.	2017-06-21 18:47:00 -04:00
Thomas Harte	108da64562	Fixed LD H, (HL) and LD L, (HL) by ensuring that whatever the subclass does goes to a temporary place before updating the address. Corrected the LD (IX+d), n machine cycle test for my new best-guess timing. This should leave only interrupt timing as currently amiss.	2017-06-20 22:25:00 -04:00
Thomas Harte	f85b46286e	Resolved the timing disparity between LD (HL),n and LD (IX+d), n, hopefully having come up with a convincing theory of timing for the latter.	2017-06-20 22:20:58 -04:00
Thomas Harte	184b371649	Attempted to get to 'proper' timing for LD (IX+d),n, albeit that proper is a guess.	2017-06-20 21:48:50 -04:00
Thomas Harte	b0375bb037	Fixed the three LD rr, (nn) operations. Back down to four FUSE failures.	2017-06-20 21:32:23 -04:00
Thomas Harte	48942848e7	Fixed (Ix+d) read timing. I've put an extra wait cycle into the read, so no need to extend the refresh.	2017-06-20 21:15:56 -04:00
Thomas Harte	27ac342928	Corrected conditional call timing, and its test.	2017-06-20 20:57:23 -04:00
Thomas Harte	25aba16ef8	Quickly checking the FUSE tests, corrected a handful of instances where PC should be modified but isn't, correcting around 800 new failures.	2017-06-19 22:20:23 -04:00
Thomas Harte	a0d0f383c8	Corrected unconditional CALL timing. Conditional's going to require more work because once the wait state is put into the right place, it breaks the assumption under which the Z80 handles conditions — that they're either do something or else do nothing. So that can wait a day.	2017-06-19 22:07:36 -04:00
Thomas Harte	cc8f316941	Resolved read-modify-write (IX+d) timing, and therefore RLC (IX+d).	2017-06-19 20:51:28 -04:00
Thomas Harte	b684254908	Introduced further tests down to a failing attempt at RLC (IX+d). Made an initial attempt to fix, failed.	2017-06-19 20:33:34 -04:00
Thomas Harte	ba15371948	Introduced timing tests for LDI[R] and CPI[R], fixing a latent issue in the rejig of LD BC, nn while I'm here.	2017-06-19 19:47:00 -04:00
Thomas Harte	73dbaebbc1	Fixed timing of EX (SP), HL/IX.	2017-06-19 19:25:53 -04:00
Thomas Harte	e3244eb68e	Rephrased internal operation machine cycles as having only an end. So they're now easy to count. Hence the test machine spots them, and a couple more of the current timing subset passes.	2017-06-19 07:39:46 -04:00
Thomas Harte	85c6fb1430	Explained refresh cycles to the all-RAM Z80.	2017-06-19 07:36:11 -04:00
Thomas Harte	54e4643396	Corrected non-default refresh cycle lengths. Reduces failures of the currently-tested timing subset from 10 to 4.	2017-06-19 07:34:23 -04:00
Thomas Harte	85c5c4405a	Ensured that wait states don't appear unless requested (TODO: requesting), and made the output of my timing tests a little easier to parse.	2017-06-19 07:30:01 -04:00
Thomas Harte	d668879ba6	Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.	2017-06-18 22:03:13 -04:00
Thomas Harte	cb140aa06e	Managed to navigate back to building.	2017-06-18 21:00:44 -04:00
Thomas Harte	6a769d3953	Finally dipped below the 20 error threshold that the compiler tops out at.	2017-06-18 20:34:46 -04:00
Thomas Harte	3be8ffd826	Some correct timings have gone out the window for now, but only the final quarter of the base page now contains compiler errors.	2017-06-18 20:31:12 -04:00
Thomas Harte	bb910e14a4	Dealt with the CB page.	2017-06-18 18:01:33 -04:00
Thomas Harte	69ebbe019a	Completed ED page conversion. Rolling onwards...	2017-06-18 17:56:48 -04:00
Thomas Harte	0d39672d32	Fixing typos here and there, persuaded the first half of the ED table to compile.	2017-06-18 17:48:54 -04:00
Thomas Harte	0d1231980a	Advanced to getting specific warnings in the ed-page table. So that's progress.	2017-06-18 17:25:15 -04:00
Thomas Harte	82a015892b	Started adapting to the newly-segmented world.	2017-06-18 17:18:01 -04:00
Thomas Harte	194b7f60c5	Rephrased to allow non-conditional waits; expanded macros to cover all permitted lengths of read and write.	2017-06-18 17:08:50 -04:00
Thomas Harte	ebc7356db5	Reformulated the machine cycle slightly to support posting operation plus phase, thereby exposing the segue points at which waits might be inserted. So: to stick to the rule that CPUs expose the minimum amount of information sufficient completely to reconstruct bus activity. This breaks the Z80 for now.	2017-06-18 12:21:27 -04:00
Thomas Harte	e1a2580b2a	Renamed BusOperation to MachineCycle::Operation.	2017-06-17 21:53:45 -04:00
Thomas Harte	efc7f9df37	Combined I and R into a register pair.	2017-06-17 18:18:28 -04:00
Thomas Harte	aed2827e7b	Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.	2017-06-12 22:22:00 -04:00
Thomas Harte	b9dbb6bcf8	Discovered my timing error: the I/R <-> A loads should take an extra cycle. This means the ZX80 now finally takes the correct 207 cycles per line. Fixed the video output wave to be clocked at the appropriate rate.	2017-06-12 18:55:04 -04:00
Thomas Harte	d12e50eb02	Corrected "should I adjust history?" tests.	2017-06-11 16:41:34 -04:00
Thomas Harte	db30f53ab0	Added the capacity to back-date interrupt line changes within a machine cycle, so that machines which time themselves entirely within perform_machine_cycle can still be cycle accurate on those changes.	2017-06-11 13:31:02 -04:00
Thomas Harte	b55579c348	Fixed usage of flush: the subclass version is definitively used.	2017-06-06 17:52:44 -04:00
Thomas Harte	3df6eba237	Fixed: my HALT line wasn't actually halting. NOPs followed, but the PC just kept counting.	2017-06-05 10:35:03 -04:00
Thomas Harte	e940e02126	Added a short circuit to set_interrupt_line, mostly to make breakpoints slightly more convenient to place.	2017-06-05 09:37:19 -04:00
Thomas Harte	7f743c6fb0	Got explicit about permitted type conversions.	2017-06-04 18:40:59 -04:00
Thomas Harte	096551ab3e	Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.	2017-06-04 18:32:23 -04:00
Thomas Harte	c485c460f7	Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.	2017-06-04 18:08:35 -04:00
Thomas Harte	d2637123c4	Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.	2017-06-04 17:55:19 -04:00
Thomas Harte	0eebfdb4cc	Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.	2017-06-04 15:39:37 -04:00
Thomas Harte	7811374b0f	Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).	2017-06-04 15:07:07 -04:00
Thomas Harte	a2f01b4a46	Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now.	2017-06-04 14:59:18 -04:00
Thomas Harte	f5c910beb7	Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE.	2017-06-04 14:18:04 -04:00
Thomas Harte	4e014ca748	Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100?	2017-06-04 14:13:38 -04:00