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9,001 Commits 8 Branches 121 Tags 496 MiB
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983 Commits

Author SHA1 Message Date
Thomas Harte
0af8660181 Remove add_pc and decline_branch in favour of operation-specific signals. 2022-05-09 16:19:25 -04:00
Thomas Harte
c61809f0c4 Add CMPAl. 2022-05-03 09:20:02 -04:00
Thomas Harte
17a2ce0464 Fix missung #undefs. 2022-05-02 21:29:46 -04:00
Thomas Harte
ef28d5512b Annotate further. 2022-05-02 12:58:04 -04:00
Thomas Harte
fa49737538 Correct processor name. 2022-05-02 08:40:47 -04:00
Thomas Harte
8a18685902 Relocated RegisterSizes to Numeric. 2022-04-28 15:10:08 -04:00
Thomas Harte
ee625cb8a8 Minor style improvements; especially: don't assume value of NoBusProgram. 2021-12-25 14:05:38 -05:00
Thomas Harte
f20940a37b Give Program full ownership of the sentinel value. 
In case I want to reduce the size of this field later.
 2021-12-23 16:32:21 -05:00
Thomas Harte
32e0a66610 Trust the compiler with this bit field. 2021-12-23 16:28:55 -05:00
Thomas Harte
d9598b35c2 Add some additional metrics. 2021-12-23 16:27:54 -05:00
Thomas Harte
0df8173536 Merge branch 'master' into Amiga 2021-11-24 08:58:03 -05:00
Thomas Harte
7e31658932 Remove accidental commit. 2021-10-26 21:49:32 -07:00
Thomas Harte
76767da300 Undo accidental change. 2021-10-25 21:48:19 -07:00
Thomas Harte
dc8701a929 Introduce some additional Blitter test cases. 2021-10-25 21:40:20 -07:00
Thomas Harte
313dbe05e0 Switch to more consistent inlining. 2021-09-23 22:36:15 -04:00
Thomas Harte
adf7124e2c Eliminate 6502Base.cpp. 2021-09-23 22:33:33 -04:00
Thomas Harte
863971f944 68000: fix E alignment, expand Microcycle::apply. 2021-09-08 21:03:37 -04:00
Thomas Harte
fd70f7ad43 Attempts to make pixel content observeable. 2021-09-08 20:57:26 -04:00
Thomas Harte
5cc25d0846 Adds a further sanity assert. 2021-08-08 21:52:52 -04:00
Thomas Harte
e402e690b0 Assume and test that divide-by-zero posts the PC of the offending instruction. 2021-08-07 17:51:00 -04:00
Thomas Harte
dcbc9847a3 Attempts to get E synchronisation correct. 2021-08-05 20:08:34 -04:00
Thomas Harte
60b09d9bb0 Increases compile-time logging options. 2021-08-01 21:22:33 -04:00
Thomas Harte
f576baf214 I'm not yet sure this is the best approach, but starts trying to make use of Lorenz's 6526 tests. 2021-07-30 21:21:16 -04:00
Thomas Harte
8d2d4c850f Revoke temporary debugging. 2021-07-25 19:59:10 -04:00
Thomas Harte
b7bed027d7 Ensures the value initially loaded to A7 is aligned. 
This is a bit of a guess; it's likely to be true though per the rule that A7 is always kept aligned.
 2021-07-25 19:55:23 -04:00
Thomas Harte
956a6dbd64 Improve commentary. 2021-07-23 19:23:54 -04:00
Thomas Harte
68fe19818e Expose more information about the E clock state. 2021-07-23 19:22:00 -04:00
Thomas Harte
69d62560b4 Adds comment to avoid potential future error. 2021-07-22 22:00:33 -04:00
Thomas Harte
26f4758523 Makes a further accommodation for PermitRead/Write. 2021-07-22 21:11:25 -04:00
Thomas Harte
5401744dc0 Add additional asserts. 2021-07-21 21:47:44 -04:00
Thomas Harte
fe10a10ac2 Correct address on stack upon priviliege exception. 2021-07-21 21:46:55 -04:00
Thomas Harte
b2ae8e7a4a Adds a type for the operation bitfield. 2021-07-18 20:54:54 -04:00
Thomas Harte
50b9d0e86d Logically, I think this should be unsigned. 2021-07-18 20:25:22 -04:00
Thomas Harte
0cfc7f732c Extends to support read/write permissions in apply. 2021-07-17 21:09:52 -04:00
Thomas Harte
51d98ef9ab Add missing stddef header where size_t is used. 2021-07-01 23:15:32 -04:00
Thomas Harte
bdcab447f9 Add a further accessor. 2021-06-27 16:27:26 -04:00
Thomas Harte
d80f03e369 Corrects longstanding deviation from naming convention. 2021-04-25 14:11:36 -04:00
Thomas Harte
e7a9ae18a1 Introduce further default state. 2021-04-24 23:18:00 -04:00
Thomas Harte
77fcf52d27 Purely style: remove some redundant nullptrs. 2021-04-19 18:53:00 -04:00
Thomas Harte
79c2bc1fd7 Put the program counter on the bus during interrupt acknowledge. 2021-04-19 18:43:50 -04:00
Thomas Harte
7017324d60 r_step is obsolete now that I know that [DD/FD]CB don't have a refresh cycle. 2021-04-13 22:17:30 -04:00
Thomas Harte
deb5d69ac7 Consolidates macros. 2021-04-13 22:11:28 -04:00
Thomas Harte
5998f3b35b Corrects LD[I/D/IR/DR] timing. 
Macro cleanup to come.
 2021-04-13 20:00:18 -04:00
Thomas Harte
869567fdd9 Corrects EX (SP), HL breakdown. 2021-04-13 19:45:48 -04:00
Thomas Harte
b42780173a Establishes that there really is no Read4 and Read4Pre distinction. 
Will finish these unit tests, then clean up.
 2021-04-12 20:54:10 -04:00
Thomas Harte
947de2d54a Switches five-cycle read to a post hoc pause. 2021-04-12 17:17:08 -04:00
Thomas Harte
e82367def3 Switches to test-conformant behaviour for (IX/IY+n) opcode fetches. 2021-04-11 23:01:00 -04:00
Thomas Harte
9cde7c12ba Shifts responsibility for refresh into the fetch-decode-execute sequence. 2021-04-11 22:50:24 -04:00
Thomas Harte
015556cc91 Switch (ii+n) to Read4Pre. 2021-04-11 10:26:14 -04:00
Thomas Harte
b397059d5e Moves read time in Read4Pre. 2021-04-10 17:54:20 -04:00