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mirror of https://github.com/TomHarte/CLK.git synced 2026-04-19 02:22:39 +00:00
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12,894 Commits 3 Branches 145 Tags
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7 Commits

Author SHA1 Message Date
Thomas Harte fb5ef200fb Correct uPD7002 interrupt wiring. 2025-09-20 21:51:19 -04:00
Thomas Harte 719a090b34 Retain bit 2. 2025-09-20 20:06:28 -04:00
Thomas Harte 3af85da6e0 Adjust conversion bits in status. 2025-09-20 19:52:47 -04:00
Thomas Harte 8fd62aa525 Disable interrupt at start of conversion. 2025-09-20 19:49:16 -04:00
Thomas Harte 421bf28582 Add comments, correct address decoding. 2025-09-18 12:27:13 -04:00
Thomas Harte 4c49ffe3d1 Attmept full ADC implementation. 2025-09-18 12:21:25 -04:00
Thomas Harte 26b1ef247b Add calls to ADB. 2025-09-17 23:11:48 -04:00