691 Commits

Author	SHA1	Message	Date
Thomas Harte	58b98267fc	Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.	2017-08-01 16:15:19 -04:00
Thomas Harte	ace71280a0	Removed implementation file; this is only ever going to be a template.	2017-08-01 16:00:17 -04:00
Thomas Harte	2b168f7383	Disabled the address sanitiser as an every-time run again, as it just pushes my computer a bit too far.	2017-07-31 22:32:56 -04:00
Thomas Harte	0536f089e1	Eliminated old-[personal-]fashioned line break.	2017-07-31 22:32:26 -04:00
Thomas Harte	3df13cddd4	As per my keenness for cleanliness improvements corresponding to my ever-increasing C++ ability: turned the Amstrad into something that a factory produces, allowing me completely to hide a bunch of implementation details.	2017-07-31 22:32:04 -04:00
Thomas Harte	68ceeab610	Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.	2017-07-31 19:56:59 -04:00
Thomas Harte	afd409c883	Ensured that ROM images are loaded and passed to the Amstrad CPC.	2017-07-31 18:44:49 -04:00
Thomas Harte	26b6c03a2a	Re-enabled the address sanitiser as a development tool.	2017-07-31 07:30:07 -04:00
Thomas Harte	c0f1313830	Performed sufficient wiring to get to the point where attempting to load a CDT creates an instance of the Amstrad CPC and then fails only because the thing vends a nullptr CRT.	2017-07-30 22:05:29 -04:00
Thomas Harte	5b5720fac0	Added to the static analyser the most basic through-path for Amstrad CPC content.	2017-07-30 21:15:20 -04:00
Thomas Harte	d25d7d7d40	Added the Amstrad CPC as a named target and declared support for its CDT file format.	2017-07-29 21:56:33 -04:00
Thomas Harte	761afad118	Corrected timestamp return, and its testing by the 6502 timing tests.	2017-07-27 21:19:16 -04:00
Thomas Harte	37950143fc	Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.	2017-07-27 20:17:13 -04:00
Thomas Harte	9257a3f6d7	Added test for 16-bit arithmetic, and fixed implementation.	2017-07-26 19:04:52 -04:00
Thomas Harte	728143247d	Added a test for RLD and RRD. Which already passes.	2017-07-26 18:56:35 -04:00
Thomas Harte	6ec4e4e3d7	Merge branch 'master' into Memptr	2017-07-25 23:01:34 -04:00
Thomas Harte	37ccb9d3b6	Fixed 6502 timing tests.	2017-07-25 23:00:39 -04:00
Thomas Harte	3c254360ba	Completed fixture of the 6502 BCD test.	2017-07-25 22:55:45 -04:00
Thomas Harte	3ca51bedc6	Discovered legitimate uses of the jam opcode so reinstated it. Corrected illegitimate uses.	2017-07-25 22:48:44 -04:00
Thomas Harte	36076b7ea5	Eliminated final vestige of professed jam handling. This should make it clear which tests still think they can capture jams.	2017-07-25 22:38:26 -04:00
Thomas Harte	279c369a1f	Switched to Cycles as the result from the 6502 perform_bus_operation, helping slightly to clarify what you're intended to return and reducing type jumping within the 6502 implementation.	2017-07-25 22:21:09 -04:00
Thomas Harte	75d67ee770	Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.	2017-07-25 20:20:55 -04:00
Thomas Harte	df4732be2e	Corrected test.	2017-07-24 22:33:49 -04:00
Thomas Harte	9435c1e12a	The 1540 is now a ClockReceiver.	2017-07-24 22:32:41 -04:00
Thomas Harte	2912d7055b	The 6532 is now a ClockReceiver.	2017-07-24 21:57:24 -04:00
Thomas Harte	13f7aa4063	The TIA is now a ClockReceiver.	2017-07-24 21:48:34 -04:00
Thomas Harte	b3ae920746	Converted the DPLL and disk controller classes to be ClockReceivers.	2017-07-24 21:04:47 -04:00
Thomas Harte	e6578defcd	It turns out that quite a few tests still rely on CSTestMachine6502JamOpcode. Though since it no longer works, that'll need to be fixed. In the meantime, fixed the test build process at least, as it's not really what this branch is meant to be invested in.	2017-07-23 22:22:50 -04:00
Thomas Harte	ace8e30818	Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.	2017-07-23 22:21:39 -04:00
Thomas Harte	b0c2325adc	Corrected run call, and accepted that jam handling is gone forever.	2017-07-22 22:21:26 -04:00
Thomas Harte	2ff157cf7a	Switched CRTMachine over to use Cycles as an explicit statement of units, and followed through on the effects of that.	2017-07-22 22:17:29 -04:00
Thomas Harte	1ba3f262a2	Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.	2017-07-22 21:46:50 -04:00
Thomas Harte	4ea835e50b	Added test for EX (SP), rp, which passes.	2017-07-22 17:17:32 -04:00
Thomas Harte	5fddbec132	Merge branch 'master' into Memptr	2017-07-22 17:06:22 -04:00
Thomas Harte	6633537fb8	Discovering that there is such a thing as P81 — a ZX81 file without the name omitted — added support for it. Extended FileHolder while I was here to retain the file name and be able to supply its extension, as my quick-fix test-the-last-character approach to o/p/80/81 discrimination stops working with p81 thrown into the mix and this feels like the correct factoring.	2017-07-22 16:02:25 -04:00
Thomas Harte	6437c43147	Added CPI and CPD tests: at last two that pass without requiring implementation changes!	2017-07-22 12:38:18 -04:00
Thomas Harte	5928a24803	Transcribed missing tests as TODOs.	2017-07-22 11:44:17 -04:00
Thomas Harte	20a6bcc676	Added tests for the various LD (nn), rr instructions and corrected implementation to pass.	2017-07-22 11:39:13 -04:00
Thomas Harte	eaf313b0f6	Added a test on LD A, (DE) and LD A, (BC), and adjusted implementation to pass.	2017-07-22 11:20:21 -04:00
Thomas Harte	d51b66c204	Expanded test to hit all 65536 possibilities (and not to allocate a fresh Z80 test machine each time, as that's unnecessary and slow), and fixed implementation to pass test.	2017-07-21 23:01:35 -04:00
Thomas Harte	660f0e4c40	Added Objective-C through wiring and a Swift test class for Memptr modifications. So far with a single test, that fails.	2017-07-21 22:52:25 -04:00
Thomas Harte	2b5d0877a8	Adjusted parameter name to match documentation. I think it's a carry-over from before I was passing the whole event along.	2017-07-21 21:27:50 -04:00
Thomas Harte	2a7fc86b15	Enabled stricter warnings.	2017-07-21 20:44:35 -04:00
Thomas Harte	8f72fc4a44	Factored out from the UEF implementation the concept of being a tape that has a queue of pending pulses and manages that queue.	2017-07-16 22:04:40 -04:00
Thomas Harte	238348c885	Performed the initial wiring to announce that this application supports TZX files and to route them to the ZX80/81 static analyser. The TZX class itself does not yet do much beyond basic validation. I think it'll be easiest if it follows in UEF's footsteps in queuing up pulses ahead of time, so some factoring out is now required.	2017-07-16 21:33:11 -04:00
Thomas Harte	7b5f93510b	Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests.	2017-07-16 20:55:57 -04:00
Thomas Harte	8ddd686049	Removed redundant variable.	2017-07-16 19:04:03 -04:00
Thomas Harte	2fb0aea990	Updated the C1540 test vessel to the new world.	2017-07-16 17:00:39 -04:00
Thomas Harte	279f4760d7	Eliminated buffer_size_ as something explicitly stored, and reduced size of delegate call out.	2017-07-16 15:01:39 -04:00
Thomas Harte	368bff1a82	Added a shell class that will one day be able to parse CSW files, plus the logic and metadata to instantiate it when a CSW presents itself.	2017-07-10 21:43:58 -04:00