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Author	SHA1	Message	Date
Thomas Harte	8c242fa2dd	Merge branch '68000Mk2' into InMacintosh	2022-06-01 10:48:38 -04:00
Thomas Harte	5a4f117a12	Merge branch '68000Mk2' of github.com:TomHarte/CLK into 68000Mk2	2022-06-01 10:48:14 -04:00
Thomas Harte	62ed1ca2fd	Fix MOVE CCR permissions.	2022-06-01 09:22:47 -04:00
Thomas Harte	d1298c8863	Correct MOVE timing without breaking PEA, LEA, etc.	2022-06-01 09:06:08 -04:00
Thomas Harte	75e85b80aa	Factor out the common stuff of exception state.	2022-06-01 08:20:33 -04:00
Thomas Harte	73815ba1dd	No need for this hoop jumping here.	2022-06-01 08:20:06 -04:00
Thomas Harte	e1abf431cb	Don't test undefined flags.	2022-05-30 16:23:51 -04:00
Thomas Harte	8e0fa3bb5f	DIV # with a divide by zero should be 44 cycles.	2022-05-29 21:22:45 -04:00
Thomas Harte	8ffaf1a8e4	Ensure did_divu/s are performed even upon divide by zero.	2022-05-29 21:18:19 -04:00
Thomas Harte	7788a109b0	Tweak more overtly to avoid divide by zero.	2022-05-29 20:51:50 -04:00
Thomas Harte	9eea471e72	Resolve infinite recursion.	2022-05-29 20:39:22 -04:00
Thomas Harte	3ef53315a2	Don't try to append operands to 'None'.	2022-05-29 15:28:16 -04:00
Thomas Harte	2a40e419fc	Fix CHK tests: timing and expected flags.	2022-05-29 15:26:56 -04:00
Thomas Harte	d6f72d9862	Avoid runtime checking of instruction supervisor requirements.	2022-05-29 14:56:44 -04:00
Thomas Harte	3da720c789	Make requires_supervisor explicitly compile-time usable.	2022-05-29 14:55:24 -04:00
Thomas Harte	dbf7909b85	Fix timing of CMPM.	2022-05-29 14:49:42 -04:00
Thomas Harte	57aa8d2f17	Correct timing of ADDQ.	2022-05-29 14:34:06 -04:00
Thomas Harte	a318a49c72	Merge branch '68000Mk2' into InMacintosh	2022-05-28 15:01:58 -04:00
Thomas Harte	35e73b77f4	Fix interrupt stack frame.	2022-05-27 21:55:17 -04:00
Thomas Harte	698d1a7111	Fix interrupt stack frame.	2022-05-27 21:54:23 -04:00
Thomas Harte	1365fca161	Avoid phoney write modifies.	2022-05-27 21:42:55 -04:00
Thomas Harte	d17d77714f	Remove outdated TODO.	2022-05-27 15:40:06 -04:00
Thomas Harte	e8dd8215ba	Tweak per empirical results.	2022-05-27 15:39:02 -04:00
Thomas Harte	e11990e453	Make an attempt at DIVS timing.	2022-05-27 15:38:54 -04:00
Thomas Harte	165ebe8ae3	Add time calculation for MULU and MULS.	2022-05-27 15:38:14 -04:00
Thomas Harte	e746637bee	Fill in dynamic cost of shifts.	2022-05-27 15:38:08 -04:00
Thomas Harte	0e6370d467	Tweak per empirical results.	2022-05-27 15:37:40 -04:00
Thomas Harte	512cd333e5	Make an attempt at DIVS timing.	2022-05-27 14:56:04 -04:00
Thomas Harte	f599a78cad	Add time calculation for MULU and MULS.	2022-05-27 14:41:42 -04:00
Thomas Harte	7601dab464	Fill in timing calculation for DIVU.	2022-05-27 14:30:03 -04:00
Thomas Harte	a8623eab4a	Fill in dynamic cost of shifts.	2022-05-27 11:12:10 -04:00
Thomas Harte	c367ddff1b	Merge branch '68000Mk2' into InMacintosh	2022-05-27 10:34:11 -04:00
Thomas Harte	67b340fa5e	Fix interrupt request address.	2022-05-27 10:33:36 -04:00
Thomas Harte	c97245e626	Fix CalcEA timing; make MOVEfromSR a read-modify-write.	2022-05-27 10:32:28 -04:00
Thomas Harte	79e2c17f93	Fix interrupt request address.	2022-05-26 20:20:28 -04:00
Thomas Harte	5937737bb7	Merge branch '68000Mk2' into InMacintosh	2022-05-26 19:37:44 -04:00
Thomas Harte	5f030edea4	Simplify transaction.	2022-05-26 19:37:30 -04:00
Thomas Harte	88e33353a1	Fix instruction and time counting, and initial state.	2022-05-26 09:17:37 -04:00
Thomas Harte	f3c0c62c79	Switch register-setting interface.	2022-05-26 07:52:14 -04:00
Thomas Harte	866787c5d3	Make an effort to withdraw from the high-circuitous stuff of working around the reset sequence.	2022-05-25 20:22:38 -04:00
Thomas Harte	367ad8079a	Add a call to set register state with population of the prefetch.	2022-05-25 20:22:05 -04:00
Thomas Harte	64491525b4	Work further to guess at caller's intention for set_state. ... Probably I should just eliminate the initial reset, somehow.	2022-05-25 17:01:18 -04:00
Thomas Harte	68b184885f	Reapply only the status.	2022-05-25 16:54:25 -04:00
Thomas Harte	06f3c716f5	Make better effort to establish initial state.	2022-05-25 16:47:41 -04:00
Thomas Harte	22714b8c7f	Capture state at instruction end, for potential inspection.	2022-05-25 16:32:26 -04:00
Thomas Harte	80c1bedffb	Eliminate false prefetch for BSR.	2022-05-25 16:32:02 -04:00
Thomas Harte	56ad6d24ee	Fix ANDI/ORI/EORI to CCR/SR timing.	2022-05-25 16:20:26 -04:00
Thomas Harte	4ad0e04c23	Fix macro for n being an expression.	2022-05-25 16:05:45 -04:00
Thomas Harte	f9d1c554b7	Fix for the actual number of cycles in a standard reset.	2022-05-25 16:05:28 -04:00
Thomas Harte	ee58301a46	Add RaiseException macro.	2022-05-25 15:45:09 -04:00