Thomas Harte
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5c68b6cc21
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Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.
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2017-07-31 22:16:08 -04:00 |
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Thomas Harte
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ffaa627820
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Fixed frame restart when there is no adjustment period.
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2017-07-31 22:13:45 -04:00 |
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Thomas Harte
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5a396f6787
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Added an explicit cast.
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2017-07-31 22:04:31 -04:00 |
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Thomas Harte
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cb0dc7b434
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I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
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2017-07-31 22:01:54 -04:00 |
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Thomas Harte
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e28829bd1b
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Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
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2017-07-31 20:14:46 -04:00 |
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Thomas Harte
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68ceeab610
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Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
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2017-07-31 19:56:59 -04:00 |
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Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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1da24d10fd
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Corrected a couple of build errors.
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2017-07-27 08:05:14 -04:00 |
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Thomas Harte
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8361756dc4
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Switched definitively to the works-for-now approach of requiring an explicit opt-in where somebody wants to clock a whole-cycle receiver from a half-cycle clock.
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2017-07-27 07:40:02 -04:00 |
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Thomas Harte
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1c2f68f129
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Removed, as it's been relocated.
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2017-07-25 20:43:05 -04:00 |
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Thomas Harte
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75d67ee770
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Relocated ClockReceiver.hpp as it's a dependency for parts of the static analyser, and therefore needs to be distinct from the actual emulation parts.
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2017-07-25 20:20:55 -04:00 |
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Thomas Harte
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a1e9a54765
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Eliminated redundant uses of ClockReceiver and sought to ensure that proper run_fors are inherited all the way down.
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2017-07-25 20:09:13 -04:00 |
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Thomas Harte
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545683df6f
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Added some documentation, got explicit again about cycle/half-cycle intermingling, and added flush as what amounts to divide(1), for cleaner usage without a clock divider.
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2017-07-25 19:50:40 -04:00 |
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Thomas Harte
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cfbd62a5dc
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Attempted to fix implementation of divide, and marked everything as-yet unmarked as inline.
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2017-07-25 07:43:39 -04:00 |
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Thomas Harte
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40339a12e1
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Formalised the use of a cycles count with a divider, bringing a few additional plain-int users into the fold.
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2017-07-25 07:15:31 -04:00 |
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Thomas Harte
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9be9bd9106
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Neatened layout.
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2017-07-24 22:52:35 -04:00 |
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Thomas Harte
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c1527cc9e2
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Reduced back-and-forth between Cycles and ints within the Oric.
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2017-07-24 22:46:31 -04:00 |
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Thomas Harte
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a1a3aab115
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Fixed implicit sign conversion.
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2017-07-24 22:40:15 -04:00 |
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Thomas Harte
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c77a83d86f
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The 6560 is now a ClockReceiver. This reduces to zero the number of remaining instances of the text run_for_cycles in this codebase.
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2017-07-24 22:38:35 -04:00 |
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Thomas Harte
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efdac2ce8c
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The 6522 is now a ClockReceiver.
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2017-07-24 22:29:09 -04:00 |
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Thomas Harte
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2912d7055b
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The 6532 is now a ClockReceiver.
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2017-07-24 21:57:24 -04:00 |
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Thomas Harte
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b7f88e8f61
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Filter is now a ClockReciever, affecting all sound output devices.
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2017-07-24 21:29:13 -04:00 |
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Thomas Harte
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8a2bdb8d22
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Converted the TimedEventLoop and the things that sit atop it into ClockReceivers.
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2017-07-24 21:19:05 -04:00 |
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Thomas Harte
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b82bef95f3
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Decided to follow through on Cycles and HalfCycles as complete integer-alikes. Which means giving them the interesting range of operators. Also killed the implicit conversion to int as likely to lead to type confusion.
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2017-07-24 20:10:05 -04:00 |
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Thomas Harte
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8a0b0cb3d7
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Extended both classes to allow copy assignment, copy construction and implicit zero-length construction.
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2017-07-23 22:13:41 -04:00 |
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Thomas Harte
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1ba3f262a2
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Sketched out a template for clock-receiving components to allow them to be implemented in terms of either half or whole cycles.
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2017-07-22 21:46:50 -04:00 |
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Thomas Harte
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8755824c64
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Added some documentation.
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2017-07-22 17:25:53 -04:00 |
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Thomas Harte
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64865b3f41
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Signedness fixes.
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2017-07-21 21:23:34 -04:00 |
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Thomas Harte
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53f0e1896b
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Made delay_time_ unsigned for safe comparison.
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2017-07-21 21:21:23 -04:00 |
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Thomas Harte
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aaa60dab12
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Fixed signedness of index.
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2017-07-21 21:21:01 -04:00 |
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Thomas Harte
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12f7e1b804
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Enshrined a default colour burst amplitude. Which now everybody relies on. The 102 figure is derived from the burst apparently being 40 IRE.
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2017-07-07 23:35:14 -04:00 |
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Thomas Harte
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eb8a2de5d6
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Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80.
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2017-05-15 07:38:59 -04:00 |
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Thomas Harte
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e270b726b3
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Tweaked blue, increased saturation.
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2017-05-13 22:01:02 -04:00 |
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Thomas Harte
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44ce7fa54c
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Corrected luminances across the board, and PAL colours.
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2017-05-13 21:50:09 -04:00 |
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Thomas Harte
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b0142cf050
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Made an updated stab at NTSC colours.
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2017-05-13 14:29:36 -04:00 |
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Thomas Harte
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a340331229
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Introduced 1-bit of saturation, returning black and white as black and white.
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2017-05-11 21:31:58 -04:00 |
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Thomas Harte
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15d17c12d5
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Switched the 6560 to two bytes per pixel, since one isn't sufficient for precision and because mixing up the implementation might help me to figure out what's amiss.
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2017-05-09 21:22:01 -04:00 |
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Thomas Harte
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5998123868
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Added some consts, for a minor safety improvement.
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2017-05-06 19:53:24 -04:00 |
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Thomas Harte
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e01f3f06c8
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Completed curly bracket movement.
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2017-03-26 14:34:47 -04:00 |
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Thomas Harte
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a4c5eebd1e
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The latest Atari Age-discovered numbers suggest this starts up in 1024T mode.
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2017-03-21 18:22:50 -04:00 |
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Thomas Harte
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c445eaec3e
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Switched startup values, following a comment on AtariAge. May or may not be correct, the thread was speculative.
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2017-03-19 17:38:26 -04:00 |
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Thomas Harte
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e0bca1e37b
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Reinstated the 16 and 32 kb Atari pagers, and ensured the 6532 always starts in a valid state.
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2017-03-18 17:34:34 -04:00 |
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Thomas Harte
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d3257c345a
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Tested against public ROMs and corrected. Also moved the deferred adjustment into a more canonical place.
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2017-03-04 17:00:28 -05:00 |
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Thomas Harte
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e09b76bf32
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Fixed 'same value, then immediate increment, then proper counting increments' behaviour and ensured it takes one cycle to commit a value. Adjusted tests to match.
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2017-03-04 15:57:54 -05:00 |
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Thomas Harte
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ced644b103
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It seems likely that an AY divides its clock by 8, not 16. I had conflated wave frequency and counter clock.
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2017-01-11 22:03:01 -05:00 |
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Thomas Harte
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eca3995481
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Added a CRC check for read address, ensured CRC, lost data and record not found are initially reset.
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2017-01-01 21:00:25 -05:00 |
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Thomas Harte
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044c920a5b
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Made it more explicit that there are no unhandled cases.
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2017-01-01 20:56:52 -05:00 |
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Thomas Harte
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0df9ce5a76
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Made an attempt at read address. So superficially that leaves only the force interrupts.
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2017-01-01 20:55:09 -05:00 |
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Thomas Harte
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f94f34f053
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Made an attempt at read track. Which means process_input_bit can't just swallow syncs any more; it now reports them as tokens of type ::Sync.
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2017-01-01 20:39:19 -05:00 |
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Thomas Harte
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c994fa39f6
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Ensured spin-up doesn't occur if there's no motor line.
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2016-12-31 16:18:30 -05:00 |
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