Thomas Harte
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4abd62e62b
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Standardises on const [Half]Cycles as the thing called and returned, rather than const [Half]Cycles & as it's explicitly defined to be only one int in size, so using a reference is overly weighty.
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2017-07-27 22:05:29 -04:00 |
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Thomas Harte
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37950143fc
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Attempted to nudge wait timing onto half-cycle boundaries, which expands the number of partial machine cycles the Z80 can post but pleasingly also regularises them. Switched the AllRAMProcessor to reporting half cycles by default and corrected all Z80 tests.
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2017-07-27 20:17:13 -04:00 |
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Thomas Harte
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847e49ccdf
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Corrected timestamp reporting by the all-RAM Z80.
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2017-07-26 19:47:39 -04:00 |
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Thomas Harte
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ace8e30818
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Bubbled the Z80's move into clock receiver territory up into the Z80 test machine.
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2017-07-23 22:21:39 -04:00 |
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Thomas Harte
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95a6b0f85c
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Introduced an NMI/wait interrupt timing test, and adjusted the Z80 to conform to information posted by Wilf Rigter.
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2017-06-22 21:09:26 -04:00 |
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Thomas Harte
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0e0ce379b4
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Renamed MachineCycle to PartialMachineCycle given that it mostly no longer intends to describe an entire machine cycle.
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2017-06-21 20:38:08 -04:00 |
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Thomas Harte
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36e8a11505
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Sought to simplify the way partial machine cycles are communicated, for ease of machine implementation. Also implemented the wait line.
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2017-06-21 20:32:08 -04:00 |
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Thomas Harte
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d668879ba6
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Started trying to wade back to passing tests. Working on the new timing tests first, and focussing on getting the Objective-C test machine to compile bus operations into machine cycles, which means indicating phase to all-RAM delegates.
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2017-06-18 22:03:13 -04:00 |
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Thomas Harte
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e1a2580b2a
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Renamed BusOperation to MachineCycle::Operation.
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2017-06-17 21:53:45 -04:00 |
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Thomas Harte
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aed2827e7b
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Implemented a rudimentary way to test that instructions take as long as the FUSE tests think they should. Hence discovered that the (HL)-accessing BIT, RES and SET weren't. Corrected.
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2017-06-12 22:22:00 -04:00 |
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Thomas Harte
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3e9212aaff
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Plumbed through to allow interrupt tests, wrote an NMI test, corrected the error revealed.
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2017-06-03 17:41:45 -04:00 |
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Thomas Harte
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d14902700a
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Minor syntax and wiring fixes.
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2017-06-01 22:33:05 -04:00 |
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Thomas Harte
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5119997122
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Made an attempt, flawed so far, to find a neat way for processor subclasses to offer bus management as an inline function.
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2017-05-30 22:41:23 -04:00 |
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Thomas Harte
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da65bae86e
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Switched to supplying the bus operation by reference, go guarantee that it isn't null.
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2017-05-30 19:24:58 -04:00 |
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Thomas Harte
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9e25d014d2
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Made an attempt to log bus activity for comparison with FUSE results.
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2017-05-22 19:49:38 -04:00 |
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Thomas Harte
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41d5dd8679
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Added a memory access delegate to the Z80 all-ram processor, to allow access patterns to be captured.
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2017-05-22 19:24:11 -04:00 |
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Thomas Harte
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7190f927b7
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Factored out the stuff that both all-RAM processors would share, rather than duplicating it.
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2017-05-16 21:28:17 -04:00 |
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Thomas Harte
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d559d8b901
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Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it.
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2017-05-16 21:19:17 -04:00 |
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