6502/CLK
1
0
Fork 0
mirror of https://github.com/TomHarte/CLK.git synced 2024-11-26 23:52:26 +00:00
Code Issues Projects Releases Wiki Activity
3,377 Commits 8 Branches 121 Tags 496 MiB
66faed4008
Commit Graph

3 Commits

Author SHA1 Message Date
Thomas Harte
b3ae920746 Converted the DPLL and disk controller classes to be ClockReceivers. 2017-07-24 21:04:47 -04:00
Thomas Harte
7b5f93510b Fixed the DigitalPhaseLockedLoopBridge bridge, once again fixing tests. 2017-07-16 20:55:57 -04:00
Thomas Harte
d1fe07f14d Added test of perfect DPLL input timing. 2016-07-12 21:42:23 -04:00