Thomas Harte
0f9ab53ea0
Resolves GCC warnings from dangling Apple IIgs work.
2021-03-21 22:36:18 -04:00
Thomas Harte
67408521cd
Makes absolutely sure not to try to use quickboot workaround for Mac 128kb/512kb.
...
Albeit that it should be harmless; it's just seeding RAM.
2021-03-06 22:34:35 -05:00
Thomas Harte
7b164de6fd
Reenables interrupts.
2021-03-06 18:53:39 -05:00
Thomas Harte
24e68166c6
Minor clean-ups of my temporary cruft.
2021-03-06 17:11:06 -05:00
Thomas Harte
b72474f418
Reduces debugging shout outs a touch.
2021-03-03 20:53:05 -05:00
Thomas Harte
38046d49aa
Increases debugging noise.
2021-03-03 20:52:14 -05:00
Thomas Harte
4601421aa6
This conditional is gone.
2021-03-03 20:52:01 -05:00
Thomas Harte
2f45e07d82
Further consolidates region map, now that shadowing is orthogonal.
2021-02-28 15:22:36 -05:00
Thomas Harte
496b6b5cfc
Introduces a further 128 bits of storage to eliminate the conditional in IsShadowed.
2021-02-28 15:14:32 -05:00
Thomas Harte
8604b1786e
Simplifies banks $02+ to a single region.
2021-02-27 23:34:51 -05:00
Thomas Harte
267e28e012
Adds various bits of debugging detritus.
2021-02-27 22:27:57 -05:00
Thomas Harte
631a8a7421
Adds bitset header.
2021-02-27 22:13:49 -05:00
Thomas Harte
7dcb0553e4
Switches to a target-centric view of shadowing.
2021-02-27 22:13:10 -05:00
Thomas Harte
2a7ea9f57c
Merge branch 'master' into AppleIIgs
2021-02-26 21:31:18 -05:00
Thomas Harte
9781460c41
Thanks to a hint from the MAME guys: finally completes Macintosh 128kb and 512kb emulation (!)
2021-02-26 21:22:35 -05:00
Thomas Harte
55c9d152e9
Slightly smarter: this does branchless shadowing without additional storage.
2021-02-24 18:46:41 -05:00
Thomas Harte
6cf9099ce1
Don't clear the mouse data full flag until both registers have been read.
2021-02-23 21:57:02 -05:00
Thomas Harte
e6dc39f6f0
Makes an attempt at mouse event transmission.
2021-02-19 22:48:15 -05:00
Thomas Harte
28ce675c96
Takes a further stab at ::CommandDataIsValid.
2021-02-19 22:22:14 -05:00
Thomas Harte
3d91b0a31b
Fixes keyboard data return.
...
Input sort of works now! Except that key repeat is way out of control.
2021-02-19 21:55:06 -05:00
Thomas Harte
5d1970d201
Adds a hacky different guess at how register access might work.
2021-02-19 21:46:18 -05:00
Thomas Harte
72d7901c88
Takes a shot at the keyboard data full flag.
...
Just a guess. But likely?
2021-02-19 20:06:12 -05:00
Thomas Harte
60cfec6a65
Amongst ever more cruft, adds a couple of extra asserts.
2021-02-18 22:49:48 -05:00
Thomas Harte
2e9065b34c
Increases number of fixed initial values.
2021-02-18 22:48:53 -05:00
Thomas Harte
e42843cca0
This may temporarily exhaust my wit for asserts.
2021-02-16 22:47:46 -05:00
Thomas Harte
3336a123f8
Asserts even more overtly.
2021-02-16 22:33:28 -05:00
Thomas Harte
28bd620e7f
Adds joystick support to the IIgs.
2021-02-16 19:39:22 -05:00
Thomas Harte
b117df3367
Factors out joystick logic.
2021-02-16 19:17:32 -05:00
Thomas Harte
fa8236741d
Takes a shot at an ADB mouse.
2021-02-15 20:49:16 -05:00
Thomas Harte
e16d5f33d1
Adds service requests. The microcontroller now appears to consume keyboard events.
2021-02-15 20:33:10 -05:00
Thomas Harte
e773b331cd
Implements register 2 listen.
2021-02-15 15:05:46 -05:00
Thomas Harte
99c21925f4
Makes attempt at keyboard mapping.
2021-02-15 15:00:12 -05:00
Thomas Harte
eccf5ca043
Makes first effort to wire up the ADB vertical blank input.
...
However: looking at the disassembly, I'm not sure it really is wired to INTR. So work to do.
2021-02-14 22:20:58 -05:00
Thomas Harte
24af62a3e5
Sets a default handler of 1.
2021-02-14 22:20:07 -05:00
Thomas Harte
52cf15c3e6
Attempts to route out modifier state.
2021-02-14 21:15:31 -05:00
Thomas Harte
a791680e6f
Implements set_status as per advice.
2021-02-14 21:04:20 -05:00
Thomas Harte
6e53b4c507
Corrects centralised ADB decoder.
...
I still think it's appropriate to do this in only a single place, given that using it is optional.
2021-02-14 20:41:05 -05:00
Thomas Harte
52c38e72f6
Starts seeking to automate register 3 handling.
...
Immediate pitfall: byte capture on the bus side isn't working correctly.
2021-02-14 20:37:33 -05:00
Thomas Harte
a51d143c35
Corrects reactive-device transmission logic.
...
Albeit that I'm still not properly responding to register 3 stuff, so the ADB bus needn't believe anything is out there. Also, without VSYNC being piped to the microcontroller it may well just not be polling anyway.
2021-02-14 18:54:22 -05:00
Thomas Harte
17e9305282
Starts adding a keyboard.
2021-02-13 23:16:45 -05:00
Thomas Harte
c284b34003
Resolves inability of ADB microcontroller to read its own ROM (!)
2021-02-13 17:53:40 -05:00
Thomas Harte
2ab3bba695
Attempts GLU register latching, restoring expected startup sequence.
2021-02-13 17:38:42 -05:00
Thomas Harte
2c4dcf8843
Edges towards implementing an ADB device.
2021-02-12 21:50:24 -05:00
Thomas Harte
ea40b2c982
Takes a stab at implementing device response.
2021-02-12 18:56:43 -05:00
Thomas Harte
adfdfa205f
Starts to establish the means by which I'll implement ADB devices.
2021-02-12 18:42:12 -05:00
Thomas Harte
33abdc95aa
Adds a helper for decoding ADB commands.
...
Still very noticeably to do: any sort of standard part for devices to respond to the bus.
2021-02-10 21:39:33 -05:00
Thomas Harte
6ca8aa99fc
Commit SDL and Qt project files; improve commenting.
2021-02-10 21:28:32 -05:00
Thomas Harte
17bac4c8cf
Starts to formalise the ADB bus.
2021-02-10 21:24:31 -05:00
Thomas Harte
46bd20b5e0
Attempts to simplify ADB bit parsing.
...
On-line output still looks reasonable, albeit that the microcontroller suddenly seems to be interested in devices F and 3 rather than 2 and 3.
2021-02-08 22:08:49 -05:00
Thomas Harte
93a80a30d3
With correct divider appears to get reset requests posted.
2021-02-07 23:05:01 -05:00
Thomas Harte
77b1efd176
Sets sensible 'reset' values.
2021-02-07 21:53:57 -05:00
Thomas Harte
acfab1dfb3
Starts to make some effort at timers.
2021-02-06 21:02:44 -05:00
Thomas Harte
b8c6d4b153
Rips out my high-level ADB microcontroller protocol implementation.
...
Adds just enough that the main computer validates the ADB controller as present and talking.
2021-01-30 17:53:27 -05:00
Thomas Harte
f50e8b5106
If I'm going to maintain the max_address approach, & is 'correct'.
...
% +1 would be 'more correct', but I think this approach is probably misguided.
2021-01-27 18:31:11 -05:00
Thomas Harte
dcc2fe0990
Improves M50470 entry-point detection, adds test output.
2021-01-26 21:29:17 -05:00
Thomas Harte
56111c75ae
Makes first efforts towards disassembly.
2021-01-26 19:52:30 -05:00
Thomas Harte
fc4bda0047
Experimentally flipping interpretation of the output bit gives something closer to coherent.
2021-01-25 22:02:39 -05:00
Thomas Harte
c8beb59172
Attempts properly to track ADB bus activity.
...
Output is not yet a valid ADB stream. Work to do.
2021-01-25 17:43:22 -05:00
Thomas Harte
8789ffda15
Corrects performer storage, RMW/W confusion, implicit casts, port readback.
2021-01-24 22:30:42 -05:00
Thomas Harte
e8e604dc3c
Attempts to wire up M50470 and GLU.
...
Resulting in an unexpected interest in R15. Bugs to find, I guess.
2021-01-24 18:07:05 -05:00
Thomas Harte
57e0fdfadc
Ensures ADB microcontroller is clocked.
...
And runs at the 'correct' speed (i.e. modulo my instruction-by-instruction implementation).
2021-01-23 22:55:12 -05:00
Thomas Harte
ec0018df79
Routes in the ADB keyboard ROM. This should get as far as parsing.
2021-01-18 16:59:49 -05:00
Thomas Harte
12784a71e2
A stab in the dark: does the IOLC inhibit also affect vector fetches?
2020-12-29 20:53:56 -05:00
Thomas Harte
114d48b076
This register appears to be read/write.
2020-12-11 21:43:34 -05:00
Thomas Harte
6e9d517c26
Minor cleanliness improvement.
2020-12-11 21:43:13 -05:00
Thomas Harte
159924dcc0
More clarity tweaks.
2020-12-10 22:47:11 -05:00
Thomas Harte
5d8f284757
Makes minor style improvements.
2020-12-10 22:11:53 -05:00
Thomas Harte
c978a95463
Increases asserts and adds a test.
...
Thereby discovers and fixes a problem with set_main_paging().
2020-12-10 21:49:23 -05:00
Thomas Harte
1928c955d9
Ensures safe startup of the Ensoniq.
2020-12-09 19:46:32 -05:00
Thomas Harte
049a78c667
Slightly restricts video flushing test.
2020-12-08 18:47:15 -05:00
Thomas Harte
65ca931e83
Throws in a new assert, against the unimplemented bit 0 of new video.
2020-12-06 20:26:24 -05:00
Thomas Harte
6cb71eb11b
This needs explicitly to be a bool for the table lookups to work.
2020-12-06 16:43:07 -05:00
Thomas Harte
43251193ee
The actual maximum line length is now 656.
2020-12-06 16:42:43 -05:00
Thomas Harte
55de98fb46
Adds a new statement of intent.
...
Now I need to try to decide whether I like my current all-in-one mapping for shadowing + paging, or whether it's better to split the things. I'm tending towards the latter at least until the functionality works.
2020-12-05 19:09:21 -05:00
Thomas Harte
1422d43c35
Corrects documentation errors and ambiguities.
2020-12-05 19:07:38 -05:00
Thomas Harte
6273ef8ba2
Adds means to force specific ROM 03 self tests.
2020-12-02 20:48:19 -05:00
Thomas Harte
3c6f09a898
Corrects super high-res aspect ratio and placement.
2020-12-02 20:47:26 -05:00
Thomas Harte
24fcb0c24b
Corrects video counter values.
...
The built-in speed test now passes.
2020-12-01 18:35:55 -05:00
Thomas Harte
03e2b6a265
Makes a slightly more rigorous attempt at discerning 1Mhz and 2.8Mhz operation.
2020-12-01 17:46:30 -05:00
Thomas Harte
ee22cf7ca1
Ensures that PAGE2 propagates from the state register to video.
2020-11-30 22:56:19 -05:00
Thomas Harte
187f507532
The soft switch is LCBANK2, not LCBANK1.
...
[This also jimmys the IIgs into always entering its extended self test, for now]
2020-11-30 22:35:51 -05:00
Thomas Harte
6000bd3a5e
Adds a bonus debugging assert. Let's see.
2020-11-30 18:15:02 -05:00
Thomas Harte
87069da3dd
Improves exposition, eliminates a couple of redundant map adjustments.
2020-11-30 18:07:03 -05:00
Thomas Harte
5cb4077576
Switches from modulo to and.
2020-11-30 17:47:57 -05:00
Thomas Harte
e9c7e0b9dd
Provisionally reverses meaning of language card RAM bank select.
2020-11-29 21:57:17 -05:00
Thomas Harte
35aa7612bb
Ensures that auxiliary/language-card soft switches don't trigger my assert.
2020-11-29 21:32:24 -05:00
Thomas Harte
acaa841822
Adds guaranteed trip to ROM for vector pulls.
2020-11-29 21:29:15 -05:00
Thomas Harte
46c1c9b5ee
CLRVBLINT calls it 3.75Hz. Which makes the arithmetic nicer.
2020-11-29 21:25:06 -05:00
Thomas Harte
4bdbca64b2
Takes a shot at the Mega II-style video interrupts.
2020-11-29 21:21:46 -05:00
Thomas Harte
11fe8ab6db
Corrects counter scales, adds a read for $c032.
...
Albeit that I have no idea what that's supposed to read as.
2020-11-29 20:08:59 -05:00
Thomas Harte
a9ce43d244
Takes a shot at the two video counter registers.
2020-11-29 19:57:35 -05:00
Thomas Harte
091bce9350
Merge branch 'master' into AppleIIgs
2020-11-29 00:09:20 -05:00
Thomas Harte
a965c8de9f
Resolves intended reset_all_keys.
2020-11-27 21:53:34 -05:00
Thomas Harte
79ef026b93
Allows machines to declare a preference for logical input.
...
It's only a preference, and the Apple II does prefer it.
2020-11-27 21:00:48 -05:00
Thomas Harte
a4ab5b0b49
Does a better job of ensuring sensible key mappings.
2020-11-27 20:49:38 -05:00
Thomas Harte
310282b7c9
Ensures extra_border_length always has a defined value.
2020-11-27 10:31:04 -05:00
Thomas Harte
af667c718e
Gets a bit more rigorous in remaining missing parts.
2020-11-26 22:36:32 -05:00
Thomas Harte
950f5b1691
Closes the loop on interrupts.
2020-11-26 19:56:42 -05:00
Thomas Harte
cbc0d848ad
Implements most of get_data.
2020-11-26 17:25:27 -05:00
Thomas Harte
f4d13d1f6f
Takes a run at the bus side of honouring Ensoniq sequence points.
2020-11-26 17:14:46 -05:00
