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Author SHA1 Message Date
Thomas Harte
d910405648 Added enough infrastructure to be able to react to the two CP/M calls this cares about. 2017-05-19 21:53:39 -04:00
Thomas Harte
62b432c046 Added the concept of a trap handler to the all-RAM processor and exposed it via the test Z80 classes. 2017-05-19 21:20:28 -04:00
Thomas Harte
eae1f78221 Implemented the main page pushes. 2017-05-19 19:28:38 -04:00
Thomas Harte
11d05fb3b8 Expanded a little on operations, added an implementation or two. 2017-05-19 19:18:35 -04:00
Thomas Harte
58efca835f Sought to add a further opcode. 2017-05-18 22:53:43 -04:00
Thomas Harte
da6e520b91 Merge branch 'master' into Z80 2017-05-18 22:30:51 -04:00
Thomas Harte
a5099f69d8 Merge pull request #127 from TomHarte/OricShift 
Maps either Mac shift key to both Oric shifts
 2017-05-18 22:27:47 -04:00
Thomas Harte
9398b6c2c8 Unable to differentiate, decided to map a Mac shift key to both Oric shifts. 2017-05-18 22:25:59 -04:00
Thomas Harte
99f2060fc1 Further improved macros. 2017-05-18 22:11:54 -04:00
Thomas Harte
5d3ebcb35a Made a first attempt at LD HL, (nn). 2017-05-17 22:42:30 -04:00
Thomas Harte
509d011fbe Implemented JP, my first Z80 operation. 2017-05-17 22:31:41 -04:00
Thomas Harte
17ffd604bf Made an attempt to get the Z80 at least as far as rejecting an opcode. 2017-05-17 21:45:23 -04:00
Thomas Harte
a3dafa9056 Abbreviated uses of enumerations. 2017-05-17 21:44:08 -04:00
Thomas Harte
21d0602305 Restored the all RAM 6502's lack of power-on reset. 2017-05-17 21:43:40 -04:00
Thomas Harte
64d6ee1be5 Adjusted slightly to adapt to latest Swift warnings. 2017-05-17 07:49:48 -04:00
Thomas Harte
1378ab7278 Ensured initial program counter and stack pointer are correct for Zexall, fixed the Z80 to use a compile-time polymorphic call for bus access. 2017-05-17 07:36:06 -04:00
Thomas Harte
87a021ec2d Made further attempt to get as fas as having the Z80 attempt to do something. 2017-05-16 22:19:40 -04:00
Thomas Harte
189317b80c Added enough of a Z80 test machine to bridge up into Swift. 2017-05-16 22:05:42 -04:00
Thomas Harte
4f0775cc7c Imported the Zexall.com tester, as a first thing to throw at the Z80 to be. 2017-05-16 21:37:09 -04:00
Thomas Harte
7190f927b7 Factored out the stuff that both all-RAM processors would share, rather than duplicating it. 2017-05-16 21:28:17 -04:00
Thomas Harte
d559d8b901 Continued edging towards getting the absolute basics of a testable Z80, for test-driven development. Corrected old-fashioned instance naming issues with the corresponding 6502 class and removed an unnecessary source file while at it. 2017-05-16 21:19:17 -04:00
Thomas Harte
2562306802 Merge branch 'master' into Z80 2017-05-16 21:05:00 -04:00
Thomas Harte
15394358df Merge pull request #126 from TomHarte/GCRAnalysis 
Corrects infinite loop when performing GCR analysis
 2017-05-16 20:54:24 -04:00
Thomas Harte
df4d4467b3 Ensured GCR parser spins the disk. 2017-05-16 20:53:06 -04:00
Thomas Harte
67ec0b9e6c Merge pull request #125 from TomHarte/SampledComposite 
Formalises reasoning for the colour phase clamp and offset...
 2017-05-16 20:47:20 -04:00
Thomas Harte
2ee8a7056e Corrected TIA no longer to assume phase is an automatic quarter askew. 2017-05-16 20:43:28 -04:00
Thomas Harte
a5075d9eb5 Formalised the reasoning behind the colour phase fix-up and made it an opt-in per-caller value. Only the Oric currently needs to opt in. 2017-05-16 20:31:39 -04:00
Thomas Harte
50bb4f0142 There's finally a loop in here, at least. 2017-05-15 22:25:52 -04:00
Thomas Harte
df80c37adb Renamed TestMachine to TestMachine6502 since there's going to be multiple of them. 2017-05-15 08:18:57 -04:00
Thomas Harte
7da51602d5 Moved flush, added run_for_cycles, which does nothing right now. 2017-05-15 07:59:21 -04:00
Thomas Harte
5152517887 Added the boilerplate stuff necessary to query registers. 2017-05-15 07:55:53 -04:00
Thomas Harte
eb8a2de5d6 Settled definitively on flush as more communicative than synchronise (and slightly more locale neutral); culled some more duplication from the Z80. 2017-05-15 07:38:59 -04:00
Thomas Harte
f2a1a906ff Adapted what negligible amount there is of the z80 as per the new CPU namespace. 2017-05-14 22:15:16 -04:00
Thomas Harte
0808e9b6fb Pulled the 6502 into a CPU namespace, making it an instance of something that has micro-opcodes and schedules them, and factoring out the formulation of a register pair. 2017-05-14 22:08:15 -04:00
Thomas Harte
b81a2cc273 First tentative steps towards adding a Z80 implementation. 2017-05-14 17:46:41 -04:00
Thomas Harte
abeaedf16f Merge pull request #123 from TomHarte/RemovedDeadOption 
Formally withdraws the 'load automatically' option for the Vic
 2017-05-14 17:03:33 -04:00
Thomas Harte
8e35e913bb Formally withdrew the 'load automatically' option for the Vic, having removed that option elsewhere. 2017-05-14 16:59:24 -04:00
Thomas Harte
81c5f4ab19 Merge pull request #122 from TomHarte/16bit6560 
Increases VIC-I intermediate format to 16 bit and corrects output colours
 2017-05-13 22:03:08 -04:00
Thomas Harte
e270b726b3 Tweaked blue, increased saturation. 2017-05-13 22:01:02 -04:00
Thomas Harte
c2b5a9bb1f Minor fix: given that phase is now a function of position, stop nudging position. 2017-05-13 21:50:48 -04:00
Thomas Harte
44ce7fa54c Corrected luminances across the board, and PAL colours. 2017-05-13 21:50:09 -04:00
Thomas Harte
b0142cf050 Made an updated stab at NTSC colours. 2017-05-13 14:29:36 -04:00
Thomas Harte
a340331229 Introduced 1-bit of saturation, returning black and white as black and white. 2017-05-11 21:31:58 -04:00
Thomas Harte
b14c892740 Switched to a safer RAII approach to this lock. 2017-05-10 21:29:39 -04:00
Thomas Harte
15d17c12d5 Switched the 6560 to two bytes per pixel, since one isn't sufficient for precision and because mixing up the implementation might help me to figure out what's amiss. 2017-05-09 21:22:01 -04:00
Thomas Harte
99800d9840 Merge pull request #121 from TomHarte/VicColours 
Permits ROM-area located PRGs that are not a power-of-two in size
 2017-05-08 22:18:47 -04:00
Thomas Harte
5d91a2600d Permitted ROM-style PRGs that are not a power-of-two in size, and added extra safety checks on loading data from a tape. 2017-05-08 22:15:35 -04:00
Thomas Harte
cb66c7e2dc Performed some minor tidying. 2017-05-08 21:05:35 -04:00
Thomas Harte
58488c93be Merge pull request #120 from TomHarte/Vic20Colours 
Corrects — and improves — Vic-20 tape loading
 2017-05-08 20:59:29 -04:00
Thomas Harte
61f8f2f18c Switched to a more straightforward way of exiting from tape data loading. 2017-05-08 20:58:55 -04:00