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11,853 Commits 10 Branches 121 Tags 500 MiB
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11853 Commits

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Author SHA1 Message Date
Thomas Harte
3a2d9c6082 Give user access to ROM; clean up a touch. 2024-03-19 20:26:17 -04:00
Thomas Harte
43a3959b8f Don't data abort on missing low ROM. 2024-03-19 15:06:01 -04:00
Thomas Harte
85a738acff Get rigorous on exception addresses. 2024-03-19 15:03:31 -04:00
Thomas Harte
17dbdce230 Eliminate SDL/scons targets for which brew is broken. 2024-03-19 14:27:46 -04:00
Thomas Harte
9d084782ae Document. 2024-03-19 12:22:19 -04:00
Thomas Harte
106937b679 Run into the shifts wall with LDR/STR. 2024-03-19 12:19:49 -04:00
Thomas Harte
623eda7162 Output branches and nops correctly. 2024-03-19 11:42:41 -04:00
Thomas Harte
2ad6bb099b Begin foray into disassembly. 2024-03-19 11:34:10 -04:00
Thomas Harte
9d858bc61b IRQ and FIQ should also store PC+4. 2024-03-18 14:08:08 -04:00
Thomas Harte
612c9ce49a Transfer logging responsibility. 2024-03-18 11:09:29 -04:00
Thomas Harte
64e025484a Adjust means of waiting out address. 2024-03-17 22:14:07 -04:00
Thomas Harte
7b1f800387 Extend I2C state machine. 2024-03-17 21:55:19 -04:00
Thomas Harte
2712d50e05 Attempt some inspection. 2024-03-16 22:02:16 -04:00
Thomas Harte
47e9279bd4 Add a target for I2C activity. 2024-03-16 15:00:23 -04:00
Thomas Harte
635efd0212 Clear keyboard interrupts. 2024-03-15 23:19:26 -04:00
Thomas Harte
1c1d2891c7 Adjust IRQ/FIQ return addresses. 2024-03-15 21:59:38 -04:00
Thomas Harte
1979d2e5ba Don't set interrupt flags before capture. 2024-03-15 21:34:39 -04:00
Thomas Harte
c25d0e8843 Correctly capture mode upon exception. 2024-03-15 18:39:56 -04:00
Thomas Harte
3a899ea4be Add test coverage for STM descending, proving nothing. 2024-03-15 14:55:17 -04:00
Thomas Harte
9d08282e28 Add enough of a keyboard to respond to reset. 2024-03-15 10:57:18 -04:00
Thomas Harte
18154278d1 Add minor note on where next. 2024-03-14 21:54:20 -04:00
Thomas Harte
9063852857 Undo spurious text change. 2024-03-14 21:16:38 -04:00
Thomas Harte
bc27e3998d Fix downward block data transfers. 2024-03-14 21:09:51 -04:00
Thomas Harte
19fa0b8945 Shush logging, momentarily. 2024-03-14 10:53:38 -04:00
Thomas Harte
4987bdfec9 Throw less. 2024-03-14 10:43:51 -04:00
Thomas Harte
0e4615564d Make bit masks easily testable; expand logging. 2024-03-13 14:31:26 -04:00
Thomas Harte
7aeea535a1 Reduce branchiness. 2024-03-13 11:02:52 -04:00
Thomas Harte
6b18d775ab Eliminate unused variables. 2024-03-12 21:53:26 -04:00
Thomas Harte
2ed031e440 Prepare for additional devices. 2024-03-12 21:23:22 -04:00
Thomas Harte
5d6bb11eb7 Add return. 2024-03-12 11:37:15 -04:00
Thomas Harte
c6b91559e1 Attempt to wire up timer interrupts. 2024-03-12 11:34:31 -04:00
Thomas Harte
6efc41ded7 Come to conclusion on R15; fix link values. 2024-03-12 10:42:09 -04:00
Thomas Harte
e9c5582fe1 Add note on ambiguity to be resolved. 2024-03-12 10:04:02 -04:00
Thomas Harte
8b3c0abe93 Take another swing at R15 as a destination. 2024-03-12 09:13:05 -04:00
Thomas Harte
a5ebac1b29 Add RISC OS 3.11 to catalogue, while bug hunting. 2024-03-11 22:19:14 -04:00
Thomas Harte
1ccfae885c Remove extra slashes. 2024-03-11 15:06:17 -04:00
Thomas Harte
971bfb2ecb Unify subtractions. 2024-03-11 14:52:48 -04:00
Thomas Harte
e7457461ba Reduce magic constants. 2024-03-11 14:49:03 -04:00
Thomas Harte
e8c1e8fd3f Fix RSB carry; unify set_pc. 2024-03-11 14:48:43 -04:00
Thomas Harte
ca779bc841 Expand test set. 2024-03-11 14:48:18 -04:00
Thomas Harte
a28c97c0de Simplify privilege test. 2024-03-11 12:14:00 -04:00
Thomas Harte
db49146efe Figure out what's going on with TEQ. 2024-03-11 09:51:09 -04:00
Thomas Harte
830d70d3aa Trust tests on immediate-opcode ROR 0; limit shift by register. 2024-03-10 23:38:31 -04:00
Thomas Harte
336292bc49 Further correct R15 as a destination. 2024-03-10 22:56:02 -04:00
Thomas Harte
bd62228cc6 The test set doesn't seem to do word rotation. 2024-03-10 22:40:37 -04:00
Thomas Harte
ccdd340c9a Reads also may or may not be aligned. *sigh* 2024-03-10 22:34:56 -04:00
Thomas Harte
0b42f5fb30 Make further test-set allowances. 2024-03-10 22:29:40 -04:00
Thomas Harte
e9e1db7a05 Change LDR writeback to destination. 2024-03-10 22:29:19 -04:00
Thomas Harte
21278d028c Correct unaligned accesses. 2024-03-10 21:56:19 -04:00
Thomas Harte
fbc273f114 Add invented model for tests. 2024-03-10 21:45:56 -04:00