Thomas Harte
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6d80856f02
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Attempts to eliminate warnings around a meaningless value and an unused label in the 8272.
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2017-11-12 16:34:51 -05:00 |
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Thomas Harte
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4778616fd7
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Eliminates unused result and unused label.
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2017-11-12 16:30:23 -05:00 |
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Thomas Harte
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5aef81cf24
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Commutes cross-platform #pragma marks to //MARK:s.
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2017-11-12 15:59:11 -05:00 |
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Thomas Harte
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2e15fab651
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Doubles down on <cX> over <X.h> for C includes, and usage of the namespace for those types and functions.
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2017-11-11 15:28:40 -05:00 |
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Thomas Harte
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5b6ea35d96
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Corrects initialisation ordering for the ZX80/81, C1540 and AY-3-8910.
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2017-11-10 22:31:27 -05:00 |
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Thomas Harte
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4cbc87a17d
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Corrects out-of-order initialisations for the 1770, Atari 2600 joystick, Pitfall II bus extender, Microdisc and 6502.
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2017-11-10 22:20:44 -05:00 |
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Thomas Harte
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ff7ba526fb
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Corrects improper initialisation order on the 6560.
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2017-11-10 22:05:35 -05:00 |
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Thomas Harte
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cb015c83e1
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Eliminated C99-style struct initialisations.
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2017-11-10 19:14:19 -05:00 |
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Thomas Harte
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c0055a5a5f
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Further builds up SConstruct, correcting many missed imports and a couple of improper uses of C99 in C++ code.
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2017-11-09 22:04:49 -05:00 |
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Thomas Harte
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f95515ae81
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Eliminates a large number of instance of end-of-line tabs.
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2017-11-07 22:51:06 -05:00 |
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Thomas Harte
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ad9df4bb90
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Commutes uint8_t *, uint16_t *, uint32_t *, size_t, off_t and long to functional-style casts.
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2017-10-21 22:30:15 -04:00 |
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Thomas Harte
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ec999446e8
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Commutes int and unsigned casts to the functional style.
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2017-10-21 21:00:40 -04:00 |
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Thomas Harte
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5e3e91373a
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Switches all unsigned int and double casts to functional style.
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2017-10-21 19:49:04 -04:00 |
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Thomas Harte
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91b867a7b3
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Ensures full 8272 instance state initialisation.
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2017-10-17 22:11:01 -04:00 |
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Thomas Harte
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3944e734d3
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Ensures full 6845 instance state initialisation and uses an unsigned shifter.
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2017-10-17 22:10:28 -04:00 |
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Thomas Harte
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97a2be71e3
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Introduces flush_tracks to Drive, while switching its interface to using Track::Address and adjusting associated integer types.
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2017-10-06 21:45:12 -04:00 |
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Thomas Harte
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edb9fd301c
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Begins this project's conversion to functional-style casts.
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2017-10-03 22:04:15 -04:00 |
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Thomas Harte
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c7f27b2db4
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Renames MFM.[c/h]pp as per its new remit: encoding only.
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2017-09-24 21:40:43 -04:00 |
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Thomas Harte
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2a08bd9ecc
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Factors shifting plus stateful [M]FM token recognition out of the MFMDiskController.
Given the proliferation of MFM-related classes, establishes a subdirectory for them.
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2017-09-24 20:07:56 -04:00 |
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Thomas Harte
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698e4fe550
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Tidies the Disk file hierarchy.
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2017-09-22 22:39:23 -04:00 |
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Thomas Harte
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d6a5f9a29e
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Revokes unnecessary change.
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2017-09-16 18:24:13 -04:00 |
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Thomas Harte
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0d84b4b9dd
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Removes some redundant end_writing calls.
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2017-09-16 17:09:17 -04:00 |
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Thomas Harte
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98751e6ac8
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Ensures that all result phases are exactly the intended length by replacing accumulation with assignment.
Also attempts a different version of control mark behaviour. Experiments.
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2017-09-15 22:59:26 -04:00 |
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Thomas Harte
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35fe4d50d4
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Adds command termination upon drive becoming unready, and copies head and drive selection into ST0.
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2017-09-15 20:26:41 -04:00 |
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Thomas Harte
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4d4a0cf1d2
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Puts the disk controller back into the loop with knowledge about reading mode, and uses that knowledge to cut off the PLL.
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2017-09-14 22:30:40 -04:00 |
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Thomas Harte
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b62f3e726a
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Adds a start-of-execution-phase get-out for drives that aren't ready.
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2017-09-12 20:43:53 -04:00 |
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Thomas Harte
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2f13517f38
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Adjusts the 1770 not to talk directly to the drive about motor status.
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2017-09-11 22:10:56 -04:00 |
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Thomas Harte
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d3c385b471
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Separates the 8272's drive selection signalling from actual drive ownership.
Thereby returns working motor control to the CPC.
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2017-09-11 21:25:26 -04:00 |
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Thomas Harte
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96bf133924
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Withdraws requirement for DiskController users to specify a PLL multiplier or to provide rotation speed.
In the latter case because it's no longer of any interest to the controller, and in the former because I'd rather it be picked automatically.
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2017-09-10 22:56:05 -04:00 |
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Thomas Harte
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0622187ddf
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Strips Controller of all capabilities now housed on the Drive.
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2017-09-10 19:23:23 -04:00 |
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Thomas Harte
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90c7056d12
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Started devolving timed event loop logic down to the drives, moving them closer to modelling real life.
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2017-09-10 14:43:20 -04:00 |
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Thomas Harte
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ff510f3b84
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Explicitly disallows copying of VIAs, and marks the constructor as noexcept.
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2017-09-05 21:21:23 -04:00 |
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Thomas Harte
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7fd6699e0b
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Corrects comment indentation.
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2017-09-05 21:15:15 -04:00 |
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Thomas Harte
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450712f39c
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Improves and corrects 6522 header documentation.
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2017-09-04 14:32:34 -04:00 |
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Thomas Harte
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24b3faa427
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Deconstitutes the 6522 into component parts, templated and non-templated.
Adjusts the Oric, Vic-20 and C-1540 accordingly, albeit with the quickest possible solutions.
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2017-09-04 14:26:04 -04:00 |
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Thomas Harte
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b30bb2a234
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Adds an initial implementation of display skew, as a completely live property.
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2017-08-29 22:16:40 -04:00 |
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Thomas Harte
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334afbc710
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Removes const from get_status and get_register, as both may now logically mutate the object.
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2017-08-27 18:13:55 -04:00 |
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Thomas Harte
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17c13624e5
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Improved comments.
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2017-08-27 18:11:40 -04:00 |
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Thomas Harte
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113349d272
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Started making some formal admissions that different CRTC models exist. Plenty yet to do.
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2017-08-27 18:10:07 -04:00 |
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Thomas Harte
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bdda701207
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Reverts previous unevidenced change.
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2017-08-26 22:58:16 -04:00 |
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Thomas Harte
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487fe83dca
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Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
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2017-08-26 17:54:54 -04:00 |
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Thomas Harte
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6c5a03187b
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Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
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2017-08-26 17:22:48 -04:00 |
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Thomas Harte
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7d7aa2f5d5
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Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
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2017-08-26 14:37:03 -04:00 |
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Thomas Harte
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28550c0227
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Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
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2017-08-26 13:56:23 -04:00 |
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Thomas Harte
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6e99169348
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Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
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2017-08-26 12:59:59 -04:00 |
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Thomas Harte
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3caa4705ca
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Limits sync counter size.
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2017-08-26 12:31:19 -04:00 |
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Thomas Harte
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039aed1bd1
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Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
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2017-08-25 21:26:01 -04:00 |
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Thomas Harte
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a914eadc85
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Ensured that register 6 is checked on every loop.
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2017-08-22 22:17:45 -04:00 |
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Thomas Harte
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e956740c56
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Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
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2017-08-22 21:54:48 -04:00 |
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Thomas Harte
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e88a51e75e
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Worked logic all the way down to the CPC. If the 8272 announces that it is asleep, it is now no longer clocked. Also very slightly cut down on IRQ line chatter to the Z80.
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2017-08-20 12:05:00 -04:00 |
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