Thomas Harte
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7399f3d798
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Caveman debugging in place, it looks like this file is returning nonsense.
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2017-06-06 18:18:55 -04:00 |
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Thomas Harte
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faeecf7665
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Made sure that there's nothing but silence at the end of the tape, even if the .O file is too long.
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2017-06-06 18:16:47 -04:00 |
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Thomas Harte
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63e0802f4e
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Ensured tape input appears on the returned value.
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2017-06-06 18:16:27 -04:00 |
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Thomas Harte
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e3ee9604a5
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Added comments.
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2017-06-06 18:01:33 -04:00 |
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Thomas Harte
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8c66e1d99d
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Factored out ZX80/81 video and rejigged to ensure it will keep ticking over irrespective of whether the machine is supplying data.
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2017-06-06 17:53:23 -04:00 |
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Thomas Harte
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b55579c348
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Fixed usage of flush: the subclass version is definitively used.
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2017-06-06 17:52:44 -04:00 |
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Thomas Harte
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ca9e8aecd6
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Made a seemingly unsuccessful attempt to add tape input.
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2017-06-06 10:13:32 -04:00 |
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Thomas Harte
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cc4cb45e9d
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Implemented keyboard input and ensured that the signal generated is marked as composite, putting the colour-suppression ball into the CRT's court.
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2017-06-06 09:25:18 -04:00 |
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Thomas Harte
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ebbf6e6133
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Surprisingly, I think this may actually be the correct output: stopped throwing away the I part of the refresh register and flipped black and white.
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2017-06-06 09:03:09 -04:00 |
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Thomas Harte
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cba07dec7e
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Doubled up to display all eight pixels. To confirm that they are the wrong pixels.
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2017-06-06 08:59:00 -04:00 |
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Thomas Harte
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6f7037b2b1
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Made an initial stab at outputting half the correct pixels.
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2017-06-06 08:55:07 -04:00 |
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Thomas Harte
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ef4b2f963d
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Probably more-or-less corrected. But this is all a bit too interdependent.
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2017-06-05 23:52:56 -04:00 |
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Thomas Harte
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97f3ff03b6
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Restored white background and attempted to correct output timing deficiencies. Incomplete success.
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2017-06-05 23:50:04 -04:00 |
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Thomas Harte
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2fbc7a2869
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Made a very basic attempt at getting something that at least demarcates proper graphics output.
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2017-06-05 23:32:49 -04:00 |
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Thomas Harte
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4983718df7
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Got to outputting something to the CRT. Should be just proper syncs and a paper background. It's not synchronising properly, so something is amiss in my timing.
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2017-06-05 10:47:42 -04:00 |
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Thomas Harte
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23ca00fd9a
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Added memory fuzzing as a way to verify state being written by the Z80. Eventually discovered the HALT problem as fixed in the last commit, so have stripped away the caveman stuff again.
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2017-06-05 10:36:07 -04:00 |
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Thomas Harte
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3df6eba237
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Fixed: my HALT line wasn't actually halting. NOPs followed, but the PC just kept counting.
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2017-06-05 10:35:03 -04:00 |
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Thomas Harte
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893f61b490
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Attempted specifically to reproduce the 1kb ZX80 memory map in the hope of getting compact lines and in case mirroring is why I'm getting completely empty video reads. Still no action.
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2017-06-05 09:38:49 -04:00 |
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Thomas Harte
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e940e02126
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Added a short circuit to set_interrupt_line, mostly to make breakpoints slightly more convenient to place.
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2017-06-05 09:37:19 -04:00 |
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Thomas Harte
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7e3a46c33e
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[Re]discovered that sync may also be a product of the interrupt cycle. So started looking into that.
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2017-06-04 21:54:55 -04:00 |
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Thomas Harte
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7f743c6fb0
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Got explicit about permitted type conversions.
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2017-06-04 18:40:59 -04:00 |
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Thomas Harte
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73654d51dd
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Wired up actually to run.
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2017-06-04 18:37:13 -04:00 |
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Thomas Harte
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096551ab3e
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Made a first attempt to hash out the ZX80's bus. Video output isn't yet going though. Can't seem to find clarity on whether horizontal sync is really programmatic. Let's see.
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2017-06-04 18:32:23 -04:00 |
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Thomas Harte
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c485c460f7
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Imported the ZX80 and 81 system ROMs (though not publicly), added enough code to post their contents into C++ world.
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2017-06-04 18:08:35 -04:00 |
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Thomas Harte
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b0a7c58287
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Fixed project to point to the XIB I actually want to keep; fixed that XIB to have the correct contents.
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2017-06-04 17:57:37 -04:00 |
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Thomas Harte
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d2637123c4
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Added necessary support to get as far as an empty window when attempting to load a piece of ZX80 software.
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2017-06-04 17:55:19 -04:00 |
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Thomas Harte
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02b7c3d1b0
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Added the necessary wiring to get into a ZX80/81-oriented part of the static analyser, which could in principle post a ZX80 target.
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2017-06-04 17:04:06 -04:00 |
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Thomas Harte
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8c1769f157
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Made a quick attempt at serialising from ZX80 .O to waves.
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2017-06-04 16:59:26 -04:00 |
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Thomas Harte
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655809517c
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Ensured that there is a subclass of file that is entrusted to load .O/.80 files, and that the code routes such files to it, noting that it should consider whether a ZX80 is required.
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2017-06-04 16:37:03 -04:00 |
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Thomas Harte
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2190f60a89
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Reinstated manual-by-stealth secondary usage of the Zexall test as a benchmarking tool.
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2017-06-04 15:46:35 -04:00 |
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Thomas Harte
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18faebc93c
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Merge pull request #130 from TomHarte/Bits35
Corrects bit 3 & 5 emulation for everything except BIT n, (HL)
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2017-06-04 15:42:22 -04:00 |
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Thomas Harte
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0eebfdb4cc
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Expanded emulation of memptr, though still incomplete. Reverted zexall tests to zexdoc. Will probably leave memptr until I've an emulated machine as test suites seem to exist, but they're machine-dependant, so figuring out how to isolate them from an architecture will be a lot easier if and when I have functioning machines.
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2017-06-04 15:39:37 -04:00 |
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Thomas Harte
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7811374b0f
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Started sneaking in memptr emulation, hopefully to get to a working BIT (hl).
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2017-06-04 15:07:07 -04:00 |
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Thomas Harte
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a2f01b4a46
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Corrected CPx bit 3 and 5 flags. I think only BIT n, (HL) with the famous MEMPTR reliance is preventing a complete pass by Zexall now.
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2017-06-04 14:59:18 -04:00 |
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Thomas Harte
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f5c910beb7
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Fixed LDIR/LDDR bit 3/5 flags. This seems once again to satisfy FUSE.
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2017-06-04 14:18:04 -04:00 |
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Thomas Harte
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4e014ca748
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Ensured BIT takes bits 5 and 3 from the computed address if used on indexed pages. That seems to cover 97 failures out of 100?
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2017-06-04 14:13:38 -04:00 |
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Thomas Harte
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87095b0578
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Undid consciously discard for bits 3 and 5 in the FUSE tests. Back to 100 failures.
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2017-06-04 14:04:26 -04:00 |
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Thomas Harte
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fba6ac2b4c
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Merge pull request #129 from TomHarte/TestMachineCommonality
Generalises the Z80 test machine's trap handler also to cover the 6502
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2017-06-03 22:27:55 -04:00 |
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Thomas Harte
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1a811b1ab1
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Eliminated the function call inherent to every decode, and also moved the fixed table of operations into a non-templated base class.
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2017-06-03 22:19:35 -04:00 |
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Thomas Harte
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c26349624c
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This, of course, should be inline to gain any benefit from the slightly-tortured private implementation.
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2017-06-03 22:00:57 -04:00 |
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Thomas Harte
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b642d9f712
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Eliminates the 6502's specialised jam handler in favour of the generic trap handler, and simplifies the lookup costs of that as it's otherwise doubling execution costs.
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2017-06-03 21:54:42 -04:00 |
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Thomas Harte
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fd6623b5a5
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Attempted to bring a common hierarchy to the Z80 and 6502 test machines, particularly with a view to eliminating the special-case Jam stuff on the 6502.
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2017-06-03 21:22:16 -04:00 |
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Thomas Harte
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0b2a3f18bc
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Merge pull request #128 from TomHarte/Scheduling
Eliminates the micro-op scheduler
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2017-06-03 20:32:39 -04:00 |
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Thomas Harte
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b304c3a4b9
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Eliminated the 6502's reliance on the micro-op scheduler.
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2017-06-03 20:30:07 -04:00 |
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Thomas Harte
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3ceef2005b
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Pulled the Z80 from the MicroOpScheduler inheritance tree as it barely uses the thing, and that allows me to make the MicroOp structure private.
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2017-06-03 19:17:34 -04:00 |
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Thomas Harte
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0f438f524b
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Merge pull request #124 from TomHarte/Z80
Introduces a decent but as-yet-imperfect implementation of the Z80 processor.
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2017-06-03 19:11:21 -04:00 |
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Thomas Harte
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24c84ca6f5
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Commented out as-yet-unimplemented features.
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2017-06-03 19:10:23 -04:00 |
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Thomas Harte
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7898f643ac
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Added bus request/acknowledge logic.
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2017-06-03 19:09:47 -04:00 |
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Thomas Harte
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7bd45d308a
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Error was simply failure of the interrupt-mode setter. Fixed.
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2017-06-03 18:58:13 -04:00 |
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Thomas Harte
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b3da16911f
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Tweaked timing of mode 0, per contradictory information. Wrote a failing test of mode 2.
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2017-06-03 18:42:54 -04:00 |
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