Thomas Harte
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5d6b5d9f10
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Eliminates all emdashes in cross-platform code.
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2018-05-13 15:34:31 -04:00 |
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Thomas Harte
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0b771ce61a
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Removes all instances of the copyright symbol.
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2018-05-13 15:19:52 -04:00 |
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Thomas Harte
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3944e734d3
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Ensures full 6845 instance state initialisation and uses an unsigned shifter.
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2017-10-17 22:10:28 -04:00 |
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Thomas Harte
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edb9fd301c
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Begins this project's conversion to functional-style casts.
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2017-10-03 22:04:15 -04:00 |
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Thomas Harte
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b30bb2a234
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Adds an initial implementation of display skew, as a completely live property.
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2017-08-29 22:16:40 -04:00 |
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Thomas Harte
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334afbc710
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Removes const from get_status and get_register, as both may now logically mutate the object.
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2017-08-27 18:13:55 -04:00 |
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Thomas Harte
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17c13624e5
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Improved comments.
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2017-08-27 18:11:40 -04:00 |
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Thomas Harte
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113349d272
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Started making some formal admissions that different CRTC models exist. Plenty yet to do.
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2017-08-27 18:10:07 -04:00 |
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Thomas Harte
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bdda701207
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Reverts previous unevidenced change.
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2017-08-26 22:58:16 -04:00 |
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Thomas Harte
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487fe83dca
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Ensures that vertical sync and end-of-visible-lines conditions potentially trigger whenever line_counter_ changes, not only when it increments.
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2017-08-26 17:54:54 -04:00 |
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Thomas Harte
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6c5a03187b
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Relocates the HSYNC start test, in order to pass Arnold's cpctest HSYNC start position conformance test.
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2017-08-26 17:22:48 -04:00 |
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Thomas Harte
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7d7aa2f5d5
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Eliminates repetition of the unpacking of register 3 into a horizontal sync count.
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2017-08-26 14:37:03 -04:00 |
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Thomas Harte
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28550c0227
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Breaks the 6845 bus cycle into a phase 1 and a phase 2 per the belief that sync line changes, which are observable, happen at the end of the first phase rather than at the beginning of the next. This may have interrupt timing effects, as machines often derive an interrupt from sync.
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2017-08-26 13:56:23 -04:00 |
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Thomas Harte
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6e99169348
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Permits the 6845's bus state to be examined by an owner, eliminating the need to buffer it in the bus handler. But more than that it allows the CRTC to decide when it adjusts the various outputs respective to the main phase. So a net effect of the change is that the CPC now sees vsync a cycle earlier, because my current reading of the 6845 datasheet is that it is set at the end of phase 1, not the beginning of the next phase 1.
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2017-08-26 12:59:59 -04:00 |
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Thomas Harte
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3caa4705ca
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Limits sync counter size.
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2017-08-26 12:31:19 -04:00 |
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Thomas Harte
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039aed1bd1
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Switches the two sync counters to upward-going rather than downward, as a more likely match to the way the rest of the 6845 implementation.
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2017-08-25 21:26:01 -04:00 |
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Thomas Harte
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a914eadc85
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Ensured that register 6 is checked on every loop.
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2017-08-22 22:17:45 -04:00 |
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Thomas Harte
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e956740c56
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Refactors the 6845 more clearly to break out the acts of ending a line and ending a frame, changing the way the memory address is altered — the end-of-line value is provisionally stored and then used if necessary — in order to do so.
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2017-08-22 21:54:48 -04:00 |
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Thomas Harte
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55055c7847
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Minor: ensured immediate line comparison works. But I think my problem might be trying to do this as straight line logic?
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2017-08-14 19:08:20 -04:00 |
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Thomas Harte
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a10389a22c
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Factored out the stuff of stuffing the bus.
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2017-08-14 12:42:22 -04:00 |
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Thomas Harte
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a5593bec79
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Threw in support for the light-pen trigger.
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2017-08-10 15:00:14 -04:00 |
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Thomas Harte
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a1e2646301
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Imposed counter size limits.
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2017-08-10 14:58:24 -04:00 |
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Thomas Harte
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6a6e5ae79c
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Forced users of the 6845 to be explicit about which type. So far with no effect.
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2017-08-10 12:28:57 -04:00 |
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Thomas Harte
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02d792c003
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Simplified logic slightly, avoiding repetition.
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2017-08-10 11:48:37 -04:00 |
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Thomas Harte
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be8e7a4144
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Eliminated false register aliasing, restricted register sizes and locked out reading and writing where appropriate.
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2017-08-10 11:22:30 -04:00 |
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Thomas Harte
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a4c910f1de
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This appears to be a more accurate take on 6845 address advancement — it is necessary that character output has finished for the line address to be updated.
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2017-08-10 11:12:53 -04:00 |
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Thomas Harte
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46278ff297
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Experimental: is this meant to be a compare-before-increment?
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2017-08-07 23:02:29 -04:00 |
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Thomas Harte
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26ce6cdab2
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Permitted register 3 to dictate vertical sync length.
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2017-08-04 08:56:36 -04:00 |
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Thomas Harte
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58b98267fc
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Formally transferred ownership of PIO accesses to an incoming template, and decided to start being explicit about how to specify the interfaces and provide fallbacks for optional behaviour for the new, clean generation of interfaces. A full-project sweep will inevitably occur but I'll try to tie off this branch first.
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2017-08-01 16:15:19 -04:00 |
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Thomas Harte
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1d99c116e7
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Actually, this is probably more correct: increment and then compare, but increment the refresh address once more after the final character, to avoid repeating it.
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2017-08-01 15:29:37 -04:00 |
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Thomas Harte
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ee27e16fb1
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Switched to post-tests increment. Seems to give proper screen width, but also eliminates that 'compare to +1' step that felt unlikely.
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2017-08-01 15:19:25 -04:00 |
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Thomas Harte
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3b1db14817
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Made a quick attempt at properly updating the refresh address.
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2017-08-01 07:36:03 -04:00 |
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Thomas Harte
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e3f677fa37
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I was under-counting row lines. Adjusted comparison. The emulator now produces a solid white square of approximately correct proportions. I'm sure that filling in pixels will reveal the next set of bugs.
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2017-07-31 22:21:46 -04:00 |
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Thomas Harte
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5c68b6cc21
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Fixed display enable reset when there's no adjustment area. A practical lesson in failure to factor.
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2017-07-31 22:16:08 -04:00 |
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Thomas Harte
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ffaa627820
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Fixed frame restart when there is no adjustment period.
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2017-07-31 22:13:45 -04:00 |
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Thomas Harte
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5a396f6787
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Added an explicit cast.
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2017-07-31 22:04:31 -04:00 |
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Thomas Harte
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cb0dc7b434
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I'm sure it's not going to be this easy, but this is a genuine attempt at full horizontal and vertical timing.
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2017-07-31 22:01:54 -04:00 |
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Thomas Harte
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e28829bd1b
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Corrected CRTC timing, gave it someone to talk to and a means with which to talk.
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2017-07-31 20:14:46 -04:00 |
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Thomas Harte
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68ceeab610
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Created a 6845 class and started pushing data at it and clocking it. It doesn't currently have the concept of a bus but will do, hence the in-header implementation.
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2017-07-31 19:56:59 -04:00 |
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