188 Commits

Author	SHA1	Message	Date
Thomas Harte	7a627b782d	Reintroduced writing of MFM sync marks when writing a sector.	2016-12-28 18:48:50 -05:00
Thomas Harte	a568172758	Made steps towards proper CRC generation. Am currently comparing against Oric disk images, as — amongst other things — they include precomputed CRCs.	2016-12-28 18:29:37 -05:00
Thomas Harte	9c0f622a2e	Started working CRC checking into the 1770. Discovered immediately that my generated CRC does not match that built into the Oric disk images. So mine is pretty-much certainly wrong. An opportunity for learning!	2016-12-26 16:46:26 -05:00
Thomas Harte	0490a47058	Worked on the all-around framework for decoding sectors back from tracks when closing down a file. Hit the wall that the parser is more observant of CRCs than the WD. No, really. So I guess I have to stop avoiding that whole issue.	2016-12-26 14:24:33 -05:00
Thomas Harte	83c433c142	Deviated from the data sheet, which seems likely to be correct. Hence removed a whole load of the temporary logging.	2016-12-26 12:48:49 -05:00
Thomas Harte	742c5df367	With lots of logging arising temporarily, fixed bug whereby conversion to a patched track would lead to holding a track with a distinct measure of time, leading to improperly-placed patches.	2016-12-25 22:00:39 -05:00
Thomas Harte	acc35885cd	Attempted to reduce track invalidations.	2016-12-25 20:38:25 -05:00
Thomas Harte	c0a1264ab0	Slightly improved legibility.	2016-12-25 20:19:47 -05:00
Thomas Harte	e2b829f68e	Made an attempt to write the proper address mark.	2016-12-25 20:15:07 -05:00
Thomas Harte	beaa868079	Factored the MFM parser out into encodings.	2016-12-25 20:00:57 -05:00
Thomas Harte	74e98fd097	Made an attempt to write actual data (albeit that CRC calculation is still missing).	2016-12-25 19:18:45 -05:00
Thomas Harte	98be6ede45	Shuffled a little to reduce risk of overflow, ensured writing is a loop, still seem to be writing too quickly for some reason.	2016-12-25 16:13:05 -05:00
Thomas Harte	d2ad2c756e	Added enough shovelling to write rubbish for an entire sector.	2016-12-25 15:46:49 -05:00
Thomas Harte	aceb7e3b6b	Started implementing write sector on the 1770, immediately deciding it would be useful to have a callback for end-of-queued-data-written from disk controller. So had a go at implementing that, naively. More investigation required.	2016-12-25 12:31:38 -05:00
Thomas Harte	901f19f89c	Added enough stuff that SSDs attached to a 1770 will now reach the entry point for writing.	2016-12-25 09:46:12 -05:00
Thomas Harte	c304db0f5a	Deintegrated the busy flag and the interrupt request line, as the latter is reset by status reads. Which also means I can start reporting the WD INTRQ line status directly from the Microdisc. That appears to be correct, rather than honouring the Microdisc IRQ select there.	2016-12-06 21:16:29 -05:00
Thomas Harte	ca50606e1d	Restored Vic audio.	2016-12-03 17:10:47 -05:00
Thomas Harte	36bc558798	Converted all 'Components' to postfix underscores.	2016-12-03 10:51:09 -05:00
Thomas Harte	81ee834530	As well as a bunch of logging, reinstated rotation position preservation across tracks.	2016-12-02 18:36:47 -05:00
Thomas Harte	93c573bfa9	Implemented missing status bits (other than the index hole), and a head loading delay for the Microdisc.	2016-12-01 21:13:16 -05:00
Thomas Harte	0a0775c3bd	Removed earlier hacky solution.	2016-12-01 20:16:11 -05:00
Thomas Harte	442986ee2c	Introduced a head loading path for 1793 machines.	2016-12-01 20:12:22 -05:00
Thomas Harte	82899f2f47	Ensured flag setting is atomic, removed duplication of interrupt request versus busy, found better names for the personality testers, unified delegate protocol.	2016-12-01 07:41:52 -05:00
Thomas Harte	b31fd11470	Fixed reporting of data request line, initial status values.	2016-11-30 22:39:55 -05:00
Thomas Harte	2222cb65d6	Split the status up into flags, assembled into a register upon demand. Attempted to implement some of the differences between the 1770/1772 and 1773/1793. Albeit with a motor fix still in place.	2016-11-30 22:26:02 -05:00
Thomas Harte	84cb07613d	Checked some documentation more thoroughly; the 1793 has quite different spin-up (/head load) semantics. So it's another distinct personality. Grrr.	2016-11-27 20:39:08 -08:00
Thomas Harte	02ba1f220f	The '72 seems to be a '70 with altered timing. So worth differentiating.	2016-11-27 21:06:17 +08:00
Thomas Harte	2c01f9dbed	Added meaningful TODOs.	2016-11-27 08:42:39 +08:00
Thomas Harte	2f459690d4	It would appear the 1770 and 1773 actually differ in relation to the (non-sensical) ability not to spin-up for a Type 2, and whether a side compare can occur. So the WD1770 class now requires a personality to be specified. Which it singly fails to honour.	2016-11-26 23:29:30 +08:00
Thomas Harte	d8ecc52de8	Temporarily disabled spin-down as harmful to the status register if following anything other than a Type 1 command.	2016-11-26 22:27:20 +08:00
Thomas Harte	b9677c9927	Consolidated interrupt request setting.	2016-11-26 09:41:53 +08:00
Thomas Harte	d5f9e0aa3b	Ensured there's no such thing as a zero-cycle operation, even if i don't yet know exactly what I should be doing.	2016-11-25 21:24:25 +08:00
Thomas Harte	4af678d2ed	Gave the Microdisc a clock signal, added just enough of force interrupt to avoid a spurious belief that a type 3 command has started.	2016-11-25 20:51:39 +08:00
Thomas Harte	d4a1961378	Added getters for the IRQ and DRQ lines plus a delegate to receive changes; adjusted code so that the two lines signal.	2016-11-21 13:21:49 +08:00
Thomas Harte	7eeaac23e7	Reversed myself. I once again do not think the clock is divided by 256 for envelopes.	2016-11-11 20:31:48 -05:00
Thomas Harte	77987bf31e	Decided to go with divide by 256 for the envelope counter after all.	2016-11-09 21:51:56 -05:00
Thomas Harte	77ce200fbb	Simplified/corrected AY tone/noise mixer logic, and made a new guess at the effect of reading registers that are smaller than 8 bits.	2016-11-09 21:21:17 -05:00
Thomas Harte	fa65cc2058	Resolved type conversion error.	2016-11-05 12:57:01 -04:00
Thomas Harte	30c670f8de	Ensured programmatic setting of the timers occurs during phase 2 _instead_ of counting.	2016-11-04 21:30:18 -04:00
Thomas Harte	21604376e6	Reintroduced clocking of the AY and boxed in the range of the master divider a little further.	2016-10-30 22:51:08 -04:00
Thomas Harte	ad00304e8a	Fixed 6522 countdown.	2016-10-28 21:05:42 -04:00
Thomas Harte	4fab794747	Added a direct-to-two-cycles emulation path for 6522 owners.	2016-10-27 21:13:25 -04:00
Thomas Harte	2eda0b3c86	Attempted to simplify the logic behind the most common 6522 usage.	2016-10-27 21:06:31 -04:00
Thomas Harte	fd823dc222	Settled on terminology.	2016-10-23 20:42:49 -04:00
Thomas Harte	b12f2f2796	Switched to more straightforward version of two-step loop, dealing with my mistaken dealing of when _master_divider&15 == 0 upon entry without adding an extra sanity check. Am also temporarily on non-modulo logic for tone generation, for a profiling test.	2016-10-23 20:32:48 -04:00
Thomas Harte	583db88299	Added a dispatch queue-powered Apple implementation of the async task queue, removed any mention of skip_samples in the AY since it isn't implemented.	2016-10-22 21:58:45 -04:00
Thomas Harte	33e628a096	Made an attempt to eliminate what amounts to manual division.	2016-10-21 22:16:44 -04:00
Thomas Harte	46a3c0922f	Slightly simplified code, fixed divider.	2016-10-21 22:12:44 -04:00
Thomas Harte	d7c0c49715	Might as well be consistent with divider loads.	2016-10-21 20:07:14 -04:00
Thomas Harte	782ef960e1	Sought both to [start to] optimise the AY and correct divider reloads. It turns out that conditionals aren't that troubling. But I can probably eliminate the counters.	2016-10-21 20:05:38 -04:00